Bit Interleaver Layout for Spreading Consecutive Bits Across Channels

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Solution Overview

Problem

Existing bit interleaving methods in digital broadcasting systems, such as DVB-T2, suffer from poor performance due to consecutive bits being transmitted through channels with low capacity, leading to errors and reduced channel capacity for lower significant bits.

Innovation Solution

A bit interleaver that permutes input bits in a block interleaver structure by flipping odd-numbered columns and cyclically shifting rows, ensuring that consecutive bits are spread across different channels with varying capacities, thereby improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional bit interleaving is used in block interleaver, then the structure is simple, but consecutive bits are transmitted through channels with low capacity leading to poor performance

Engineering Contradiction:
Improvebit transmission reliabilityVSAvoidinterleaving structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the bit stream by dividing it into multiple groups based on significance (first group of most significant bits, second group of less significant bits, etc.). This segmentation allows different groups to be interleaved independently, ensuring that consecutive bits within each group are spread across different channels, thereby improving reliability without requiring complete restructuring of the entire system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different interleaving strategies to different groups of bits based on their significance. More significant bits receive more robust interleaving treatment to ensure they are transmitted through higher capacity channels, while less significant bits use standard interleaving. This local differentiation improves overall reliability by optimizing protection for critical data without unnecessarily complicating the handling of all bits.

Inventive Principle:
Principle #3Local quality

2Reliability

If bits are transmitted sequentially through channels, then the transmission process is simple, but consecutive bits experience low channel capacity leading to errors

Engineering Contradiction:
Improveerror resistanceVSAvoidtransmission efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces a new dimension of interleaving by organizing bits into significance-based groups and applying group-specific interleaving patterns. This transforms the traditional single-dimension sequential transmission into a multi-dimensional structure where bits are distributed across both channel sequences and significance groups, ensuring better error resistance while maintaining efficient transmission through structured organization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If all bits are treated equally in interleaving, then the processing is simple, but lower significant bits suffer from reduced channel capacity

Engineering Contradiction:
Improvechannel capacity utilizationVSAvoidinterleaving processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different interleaving strategies to different groups of bits based on their significance. More significant bits receive more robust interleving treatment to ensure they are transmitted through higher capacity channels, while less significant bits use standard interleaving. This local differentiation improves overall reliability by optimizing protection for critical data without unnecessarily complicating the handling of all bits.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the interleaving parameters (such as interleaving depth, group size, and distribution patterns) based on the significance of different bit groups. By dynamically adjusting these parameters according to bit importance, the system optimizes channel capacity utilization for each group, ensuring that critical bits receive enhanced protection while maintaining efficient processing overall.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10236919B2Bit interleaver and bit de-interleaver
Publication Date: 2019.03.19 SAMSUNG ELECTRONICS CO LTD
  • US10236919B2 patent drawing
  • US10236919B2 patent drawing
  • US10236919B2 patent drawing

AI summary

A method for bit interleaving is provided. A method includes mapping a set of bits a≡{ak: k=0, 1, 2, . . . Npost−1} to an array B={Bi,j: i=0, 1, 2, . . . , M−1; j=0, 1, 2, . . . , N−1} such that bit ak maps to Bk mod M, └k/M┘, wherein mod denotes the modulo operator, └┘ denotes the floor operator, and M and N are constants, performing at least one of—a first permutation operation comprising permuting two or more bits within each of one or more first groups of bits, wherein each first group of bits is defined by G(1)p={Bi,p: i=0, 1, 2, . . . , M−1; p∈{0, 1, 2, . . . , N−1}} and—a second permutation operation comprising permuting two or more bits within each of one or more second groups of bits, wherein each second group of bits is defined by G(2)q={Bq,j: j=0, 1, 2, . . . , N−1; q∈{0, 1, 2, . . . , M−1}} and de-mapping bits from B to obtain an interleaved set of bits b≡{bk: k=0, 1, 2, Npost−1} such that bit Bi,j is de-mapped to bit bNi+j.