Bit Interleaving for Rotated Constellation LDPC Reception
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Solution Overview
Problem
The configuration of receivers becomes complex due to interleaving of codeword bits without consideration of the number of dimensions D, leading to inefficiencies in handling various dimensions, particularly in systems employing rotated constellations with quasi-cyclic low-density parity-check codes.
Innovation Solution
A new interleaving method is introduced where the codeword is divided into sections such that each section consists of B×D quasi-cyclic blocks, with a bit permutation that maps Q bits to Q different groups, allowing for efficient mapping and rotation of D-dimensional vectors using an orthogonal matrix, thereby simplifying the receiver configuration across different dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If interleaving of codeword bits is performed without consideration of the number of dimensions D, then the transmission can be performed with various rotated constellations, but the receiver configuration becomes complex
Solution Approach 1:
The codeword is divided into multiple sections, where each section contains a specific number of quasi-cyclic blocks (B×D blocks). This segmentation allows the transmitter to organize bits in a structured manner that aligns with the D-dimensional vector groups, enabling the receiver to process each section independently with a standardized configuration regardless of the total number of dimensions.
Solution Approach 2:
The bit permutation is performed in advance at the transmitter side according to a predetermined rule that maps Q bits to Q different groups. This preliminary organization of bits ensures that when the receiver receives the signal, the bits are already arranged in a format that corresponds to the D-dimensional vector structure, eliminating the need for complex adaptive configuration at the receiver.
2Device complexity
If D-dimensional vectors are formed from B×D quasi-cyclic blocks with bit permutation, then the receiver configuration is simplified, but the interleaving process becomes more structured
Solution Approach 1:
The invention changes the parameters of the interleaving process by defining specific relationships between the number of quasi-cyclic blocks per section (B×D), the bits per block (Q), and the dimensions (D). By establishing these parameter relationships, the bit permutation follows a systematic pattern that, while structured, uses consistent mathematical relationships that simplify both implementation and receiver design.
3Productivity
If sections are divided into B×D quasi-cyclic blocks with specific bit permutation, then efficient mapping and rotation is achieved, but the initial codeword organization becomes more complex
Solution Approach 1:
The codeword is segmented into sections, with each section containing exactly B×D quasi-cyclic blocks. This segmentation creates natural boundaries that align with the D-dimensional vector structure, allowing efficient parallel processing of multiple sections and enabling the mapping and rotation operations to be performed systematically on each section independently.
Solution Approach 2:
The bit permutation is performed as a preliminary step before mapping and rotation, organizing the bits into the required structure in advance. This preliminary organization ensures that when the mapping and rotation operations are performed, the data is already in the optimal format, maximizing the efficiency of these subsequent operations.
Data Source
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AI summary
A codeword is divided into N/(B×D) sections, a bit permutation is applied to (B×D)×Q bits of each of the sections, each Q groups of bits of each of the sections are mapped to a real-valued symbol, each Q D-dimensional vector having D real-valued symbols in Q×D real-valued symbols of each of the sections is multiplied by an orthogonal matrix with D rows and D columns, only two bits of the same quasi-cyclic block are encoded in a constellation block consisting of two D-dimensional vectors, and the two bits are mapped to the same dimension of the two D-dimensional vectors one bit by one bit.