Bit Inversion for Memory Repair Indication
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Solution Overview
Problem
Existing memory systems face challenges in efficiently indicating failed access lines during repair operations, as setting a large quantity of one-time programmable (OTP) elements to indicate addresses can lead to prolonged repair durations and high latency.
Innovation Solution
The implementation of bit inversion techniques in memory systems, where the address of a failed access line or its inversion is stored based on the quantity of bits with a logic value, reduces the number of OTP elements that need to be set, thereby shortening repair durations and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large quantity of OTP elements are set to indicate the address of a failed access line, then the accuracy of failure indication is improved, but the repair duration and latency increase
Solution Approach 1:
The patent applies bit inversion to the address representation. Instead of setting OTP elements to indicate the actual failed address directly, the system inverts the bits of the address and uses that inverted representation to index into a lookup table. This allows the system to reduce the number of OTP elements that need to be set while maintaining accurate failure indication, as the inverted address provides a compact representation that maps to the correct repair information in the lookup table.
Solution Approach 2:
The patent segments the address indication process into two parts: a compressed representation using fewer OTP elements, and a lookup table that stores the mapping between the compressed representation and the full repair information. This segmentation allows the system to use a small number of OTP elements for indication while the lookup table provides the detailed repair information, resolving the contradiction between indication accuracy and repair time.
2Loss of information
If a large quantity of OTP elements are set to indicate the address of a failed access line, then the completeness of repair information is improved, but the latency for repair operations increases
Solution Approach 1:
The patent implements preliminary action by pre-computing and storing the mapping between inverted addresses and repair information in a lookup table during system initialization or idle time. This allows the actual repair operation to simply involve reading from the lookup table rather than processing a large quantity of OTP elements, significantly reducing repair latency while maintaining information completeness.
Solution Approach 2:
The patent creates a copy of the repair information in the lookup table that can be quickly accessed during repair operations. Instead of directly reading from a large number of OTP elements during the critical repair path, the system uses the inverted address to index into a pre-organized copy of the information in the lookup table, reducing the time required to retrieve complete repair information.
3Productivity
If bit inversion is applied to reduce the number of OTP elements set, then the repair duration is reduced, but the complexity of address processing increases
Solution Approach 1:
The patent implements self-service by having the address inversion and lookup table indexing operations performed automatically by the memory controller during normal operation. The controller seamlessly handles the inversion and lookup without requiring manual intervention or complex external processing, thereby achieving faster repair speeds while the added complexity is contained within the controller's automated logic.
Data Source
AI summary
Methods, systems, and devices for bit inversion techniques for memory system repair indications are described. A memory system may store an address of a failed access line or an inversion of the address based on a quantity of bits having a first bit value. For example, if an address has a quantity of ‘1’s that is greater than a threshold, the memory system may store an inversion of the address by inverting the address and setting one-time programmable (OTP) elements to indicate the inverted ‘1’s. The memory system may also store an additional inversion bit to indicate the inversion of the address. For reading the OTP elements, the memory system may interpret an address as inverted or non-inverted based on the inversion bit. The memory system may also indicate one or more steps of a repair process to a host system to facilitate communication during repair procedures.