Noise Cancelling Circuit Using Bit Inversion for Power Noise Suppression
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Solution Overview
Problem
Existing noise cancelling circuits face difficulties in generating noise cancelling signals at higher operation speeds due to increased complexity in timing design, especially with high-speed data communication, where power source noise suppression is challenging near resonance frequencies.
Innovation Solution
A noise cancelling circuit design that includes a first and second parallel-serial conversion circuit, inverting circuit, and buffers connected to a common power source and ground, generating noise cancelling signals by inverting odd and even bits of parallel data, allowing for reduced instantaneous current noise and effective power source noise suppression without requiring high-speed clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional noise cancelling circuits use high-speed clock signals and flip-flop circuits for generating noise cancelling signals, then noise cancellation can be achieved, but the timing design complexity dramatically increases with higher data communication speeds
Solution Approach 1:
The patent replaces the conventional approach using high-speed clock signals and flip-flop circuits with a parallel-serial conversion circuit system. Instead of relying on high-speed synchronous timing mechanisms, the invention uses parallel data processing followed by serial conversion, eliminating the need for complex high-speed timing design while maintaining noise cancellation effectiveness.
Solution Approach 2:
The patent divides the data processing into parallel channels that are processed simultaneously, then converted to serial output. By segmenting the data path into multiple parallel streams that can be independently processed and then recombined, the system avoids the timing complexity of high-speed single-channel processing while achieving the same noise cancellation goal.
2Productivity
If data communication speed is increased to meet higher data communication capacity demands, then data communication capacity improves, but instantaneous current increases making power source noise suppression more difficult
Solution Approach 1:
The patent employs periodic switching of the parallel-serial conversion circuit blocks, activating them in alternating sequences. This periodic operation allows the system to handle high data communication capacity while distributing the instantaneous current demand over time, preventing current spikes that would excite power source impedance resonance and generate noise.
Solution Approach 2:
The system dynamically switches between different parallel-serial conversion circuit blocks based on operational requirements. By dynamically activating specific circuit blocks in a controlled sequence rather than operating all circuits simultaneously at full speed, the system maintains high data throughput while managing instantaneous current consumption to avoid power source noise.
Data Source
AI summary
A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.