Bit-Level Block Transfer Hardware for Display Plane Compositing
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Solution Overview
Problem
In small computer systems, such as mobile devices and thin-client terminal systems, the task of rendering full-motion video is challenging due to limited CPU power, memory, and video display adapter resources, leading to high memory bandwidth requirements that hinder functionality.
Innovation Solution
The implementation of enhanced bit-level block transfer hardware and matrix-based techniques for compositing images from display planes, which optimizes memory bandwidth by efficiently transferring and blending data between planes, reducing the need for frequent memory accesses and CPU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If full-motion video is decoded and merged with frame buffer data in small computer systems, then video display functionality is achieved, but memory bandwidth requirements become excessively high
Solution Approach 1:
The patent segments the display rendering process into separate display planes (e.g., background plane, foreground plane, video plane) that can be independently processed and stored in memory. Each plane contains specific types of display data (static backgrounds, interactive elements, video content), allowing the system to process and transfer only the necessary plane data rather than the entire frame buffer, thereby reducing memory bandwidth requirements while maintaining full video display functionality.
2Manufacturing precision
If CPU processes all video decoding and compositing tasks, then display quality is maintained, but CPU power consumption increases beyond available resources
Solution Approach 1:
The patent introduces a dedicated video display adapter as an intermediary device between the CPU and display output. This adapter contains specialized hardware circuits for video decoding, plane compositing, and blending operations. The CPU only needs to prepare and transfer data to the adapter, while the adapter handles the computationally intensive video processing tasks, thereby maintaining display quality while reducing CPU power consumption to levels suitable for small computer systems.
3Productivity
If more memory is allocated for video processing, then video rendering performance improves, but system cost and complexity increase
Solution Approach 1:
The patent merges multiple display-related functions into a unified display plane architecture. Multiple planes (background, foreground, video, cursor) are combined through hardware compositing operations rather than requiring separate memory allocations for each function. The system uses bitwise logical operations (OR, AND, XOR) and alpha blending to composite planes, allowing efficient video rendering with minimal memory resources and reduced system complexity compared to traditional approaches that require separate buffers for each display element.
Data Source
AI summary
Systems and methods for compositing an image from display planes are disclosed. An internal matrix having transparency data indicating transparency of a macro block of a digital representation of a display is accessed. An external matrix is accessed if the internal matrix indicates the macro block includes a transparent and opaque pixel, wherein the external matrix has transparency data indicating transparency of each pixel in the macro block. A first display plane is read based on the transparency data indicating opaque pixels and the first display plane data is sent to a first buffer. Second display plane data of a second display plane is read and sent to a second buffer if the transparency data indicates transparent pixels. Control data is inserted into the first buffer accordingly such that an image is generated based on at least one of the first and second display plane data and the control data.