Bit Line Air-Gap Structure for Lower DRAM Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices miniaturize and integrate more densely, parasitic capacitance between conductive materials, such as bit lines and contact plugs, becomes a significant limiting factor in device performance, particularly in DRAMs.
Innovation Solution
A semiconductor structure is manufactured with a bit line array where bit lines are connected through support patterns and feature bit line side walls composed of a first side wall dielectric layer, an air gap, and a second side wall dielectric layer, which are stacked in sequence. This structure reduces parasitic capacitance by creating air gaps between dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are miniaturized and arranged at high density, then integration density is improved, but parasitic capacitance between conductive materials increases
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent bit lines and replaces it with air gaps. By removing the solid dielectric layer in specific regions and replacing it with air (vacuum), the parasitic capacitance between conductive lines is reduced while maintaining the high-density interconnection structure.
Solution Approach 2:
The patent applies different dielectric properties to different regions of the interlayer dielectric structure. Air gaps are introduced in regions where bit lines are in close proximity to reduce parasitic capacitance, while solid dielectric material is retained in other regions to provide mechanical support and insulation where needed.
2Reliability
If air gaps are introduced to reduce parasitic capacitance, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates air gap formation into the existing multi-layer dielectric stacking process. The sacrificial layer is deposited and patterned along with the dielectric layers in a coordinated sequence, allowing air gaps to be created during the normal fabrication flow without requiring separate, complex post-processing steps.
Solution Approach 2:
The patent uses a sacrificial layer as an intermediary material to define the air gap regions. This sacrificial layer is temporarily deposited and patterned to mark where air gaps should form, then removed to create the air gaps. This approach simplifies the process by using a familiar deposition and etching sequence rather than requiring direct air gap formation techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of air gaps between dielectric layers decreases the overall dielectric constant of interlayer dielectric layers, thereby reducing parasitic capacitance and enhancing the performance of semiconductor devices.
Implementation Method 1
The introduction of air gaps between dielectric layers decreases the overall dielectric constant of interlayer dielectric layers, thereby reducing parasitic capacitance
Data Source
AI summary
The present disclosure relates to a method for manufacturing a semiconductor structure, the method includes: a substrate is provided; a bit line array is formed on an upper surface of the substrate, the bit line array includes several bit lines arranged at intervals, the bit lines are connected through at least one support pattern, and the at least one support pattern penetrates through the bit line array along an arrangement direction of the bit lines; a bit line side wall is formed on side walls of each of the bit lines; a part of the at least one support pattern is removed so as to expose at least one sacrificial layer; and the at least one sacrificial layer is removed, so as to form at least one air gap between the first side wall dielectric layers and the second side wall dielectric layers.