Bit Line Spacer Air Gap Structure for Low Parasitic Capacitance
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Solution Overview
Problem
The challenge of forming structurally complete air gaps in semiconductor devices to reduce parasitic capacitance and improve etching selectivity is significant, especially with the decreasing critical dimensions in highly integrated semiconductor devices.
Innovation Solution
A semiconductor device is manufactured with spacers made of low-k materials like silicon carbide and nitride, where an air gap is formed between these spacers, sealed by a cover layer, to reduce parasitic capacitance and enhance etching selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If etching process is performed to create airgaps in highly integrated semiconductor devices, then parasitic capacitance is reduced, but etching selectivity deteriorates leading to leakage and parasitic capacitance fail
Solution Approach 1:
The airgap formation process is divided into multiple selective etching steps with different etchants. First, a mandrel is formed and coated with a first spacer material. Then a first etching process removes the mandrel material while preserving the spacer. Subsequently, a second etching process creates the final airgap. This segmentation allows each etching step to have optimized selectivity for its specific purpose, preventing leakage while achieving the desired airgap structure.
Solution Approach 2:
A mandrel structure serves as an intermediary element during the airgap formation process. The mandrel is first formed to define the airgap location, then a spacer material is deposited on it. The mandrel is selectively removed to create the airgap, leaving the spacer in place as the final structure. This intermediary approach enables precise control over airgap formation while maintaining high etching selectivity throughout the process.
2Productivity
If distance between conductive structures is decreased for high integration, then device integration is improved, but airgap formation becomes more difficult due to poor etching selectivity
Solution Approach 1:
Different regions of the semiconductor structure receive different treatments during airgap formation. The spacer material is selectively deposited only on specific surfaces (e.g., sidewalls of mandrels) while leaving other regions unchanged. Subsequent selective etching processes remove materials from specific locations while preserving others. This local quality approach enables airgap formation in highly integrated devices by precisely controlling where airgaps are created without affecting adjacent conductive structures.
Solution Approach 2:
The etching process parameters are changed between different steps to achieve optimal selectivity at each stage. Different etchants, temperatures, pressures, and power levels are used for mandrel removal versus final airgap creation. By dynamically adjusting process parameters, the method maintains ease of manufacture even as device integration increases and feature sizes decrease, ensuring reliable airgap formation throughout the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance and improves the integrity of air gaps, enhancing the stability and reliability of semiconductor devices by using spacers with high etching selectivity and controlled oxidation processes.
Implementation Method 1
An oxidation process is performed to the first spacer such that a surface portion of the first spacer is transformed to an oxide spacer, wherein the oxide spacer is oxidized by the oxidation process
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first spacer on a bit line, wherein the first spacer includes low-k material doped with carbon. An oxidation process is performed to the first spacer such that a surface portion of the first spacer is transformed to an oxide spacer. The first spacer has a remaining first spacer that is not oxidized by the oxidation process. Then, a second spacer is formed on the oxide spacer, wherein the second spacer includes nitride. The oxide spacer is removed to form a gap between the remaining first spacer and the second spacer. A cover layer is formed to cover the bit line, the remaining first spacer, and the second spacer such that an air gap is sealed by the cover layer, the remaining first spacer, and the second spacer.