Bit Line Alignment for Soft Error Reduction

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Solution Overview

Problem

As integrated circuits shrink, they become more susceptible to radiation-induced faults like single-event upsets (SEUs) and multi-bit upsets (MBUs), which are difficult to detect and correct without substantial overhead using current error control techniques.

Innovation Solution

The method involves modifying the chip design to rotate word lines from a gravitational direction to a direction perpendicular to it, reducing the likelihood of radiation-induced errors by altering the orientation of elements in the integrated circuit during fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If advanced error correction techniques are used to detect and correct radiation-induced faults, then reliability is improved, but device complexity and overhead increase substantially

Engineering Contradiction:
Improvefault detection and correction capabilityVSAvoidoverhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the physical orientation parameter of word lines from gravitational direction to perpendicular direction, which modifies the interaction characteristics with radiation particles. This parameter change reduces susceptibility to radiation-induced faults without requiring complex error correction circuitry, thereby improving reliability while avoiding substantial overhead

Inventive Principle:
Principle #35Parameter changes

2Productivity

If integrated circuit size is reduced to continue scaling, then productivity and integration density are improved, but susceptibility to radiation-induced faults increases

Engineering Contradiction:
Improveintegration densityVSAvoidradiation susceptibility
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By changing the orientation parameter of word lines to be perpendicular to the gravitational direction, the patent reduces the effective cross-section for radiation particle interactions. This allows continued circuit scaling and integration density improvement while mitigating the increased radiation susceptibility that normally accompanies size reduction

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240184971A1Bit line alignment for the reduction of soft errors
Publication Date: 2024.06.06 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20240184971A1 patent drawing
  • US20240184971A1 patent drawing
  • US20240184971A1 patent drawing

AI summary

A method for bit line alignment during the design of an integrated circuit is provided. Aspects include receiving a chip design for the integrated circuit and receiving an intended orientation of the integrated circuit. Aspects also include identifying one or more elements of the chip design that include word lines that are oriented in a substantially gravitational direction and modifying the chip design to perform one or more of rotating the one or more elements such that the word lines are no longer oriented in a substantially gravitational direction and rotating the one or more elements such that the word lines are oriented in a direction substantially perpendicular to the gravitational direction. Aspects further include causing the fabrication of the integrated circuit based on the modified chip design.