Bit Line Bias Circuit for Memory Reading Time Reduction
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Solution Overview
Problem
In memory systems, the resistive and capacitive characteristics of bit lines lead to unpredictable settling times, increasing reading time, and the pre-charging ability decreases as the bit line voltage approaches the desired level, affecting sensing accuracy.
Innovation Solution
A memory system incorporating a voltage bias transistor, page buffer, common source transistor, and bias circuit with a charging current reproduce unit, cell current reproduce unit, current comparator, and bit line bias generator to dynamically adjust the bit line bias voltage based on the charging status, ensuring consistent pre-charge and sense operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bit line is pre-charged with a master-slave transistor controlled by a predetermined voltage, then the pre-charge operation can be performed, but the charging ability decreases as the voltage of the bit line approaches the desired level, which increases the reading time
Solution Approach 1:
The patent applies dynamics by making the charging current adjustable rather than fixed. The master-slave transistor structure allows the charging current to be dynamically controlled in two phases: initially providing high current for fast charging when the bit line voltage is low, then reducing current as the voltage approaches the target level, preventing overshoot and reducing settling time.
Solution Approach 2:
The patent implements periodic action through the master-slave transistor switching mechanism. The master transistor activates first to provide initial charging current, then switches off when the bit line voltage reaches a threshold. Subsequently, the slave transistor activates to provide continued charging with different current characteristics, creating a staged periodic charging sequence that optimizes both speed and accuracy.
2Measurement precision
If the worst case settling time is always applied to ensure the sensing accuracy, then the sensing accuracy can be maintained, but the reading time increases due to process variations
Solution Approach 1:
The patent applies feedback by using the bit line voltage level itself as a control signal for the master-slave transistor switching. When the bit line voltage reaches a predetermined threshold during charging, this voltage level triggers the master transistor to switch off and the slave transistor to activate. This feedback mechanism ensures the charging process adapts to actual voltage conditions, maintaining sensing accuracy while avoiding unnecessary charging time based on worst-case assumptions.
3Ease of operation
If the bit line is resistive and capacitive due to inevitable parasitic resistors and capacitors, then the bit line can be charged, but the settling time of the bit line contributes to a significant part of the total reading time
Solution Approach 1:
The patent applies parameter changes by modifying the charging current parameters dynamically during the pre-charge operation. The master-slave transistor configuration enables the system to change current magnitude and sourcing characteristics based on the charging stage, effectively compensating for the fixed parasitic RC time constants of the bit line and reducing the overall settling time contribution to reading operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution optimizes pre-charge time by maintaining strong charging ability and detecting charging status, reducing the impact of process variations and improving reading time accuracy.
Implementation Method 1
The voltage bias transistor has a first terminal for receiving a first system voltage, a second terminal, and a control terminal for receiving a first bias voltage. The page buffer charges the first bit line to the first system voltage according to a bit line bias voltage during a pre-charge operation
Implementation Method 2
The current comparator is coupled to the charging current reproduce unit and the cell current reproduce unit. The current comparator includes a first current generator, and a second current generator. The first current generator generates a replica charging current according to the charging reference voltage, and the second current generator generates a replica cell current according to the cell reference voltage
Data Source
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AI summary
A bias circuit includes a charging current reproduce unit, a cell current reproduce unit, a current comparator, and a bit line bias generator. The charging current reproduce unit generates a charging reference voltage according to a charging current flowing through a voltage bias transistor. The cell current reproduce unit generates a cell reference voltage according to a cell current flowing through a common source transistor. The current comparator includes a first current generator for generating a replica charging current according to the charging reference voltage, and a second current generator for generating a replica cell current according to the cell reference voltage. The bit line bias generator generates a bit line bias voltage to control a page buffer for charging a bit line according to a difference between the replica charging current and the replica cell current.