Bit Line Buffer Structure for Scaled Buried Contact Arrays
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Solution Overview
Problem
The increasing complexity and difficulty in forming wiring lines and buried contacts in highly scaled semiconductor devices due to reduced design rules complicates the manufacturing process and affects product reliability.
Innovation Solution
A semiconductor device design featuring a device isolation layer defining a cell active area, with buried contacts and bit line structures that include a T-shaped buffer pattern, along with specific arrangements of gate electrodes, landing pads, and capacitor structures to enhance electrical connections and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design rules are reduced to increase device integration, then the number of semiconductor devices in the same area increases, but the complexity and difficulty of forming wiring lines and buried contacts increases
Solution Approach 1:
The bit line structure is divided into multiple segments: bit line contact portion, bit line pass portion, and extended bit line portion. This segmentation allows each part to be formed with appropriate process conditions, simplifying the overall manufacturing process while maintaining high integration density
Solution Approach 2:
The patent introduces a three-dimensional structure with buffer patterns having different heights and shapes (T-shaped, L-shaped) to manage the complexity of wiring and contacts. The buffer patterns extend in multiple directions and have varying elevations, allowing complex electrical connections to be achieved through vertical and horizontal dimensionality rather than planar complexity alone
2Area of stationary object
If design rules are reduced to increase device integration, then more devices fit in the same area, but manufacturing process difficulty increases
Solution Approach 1:
Buffer patterns are formed in advance before the bit line structure is created. These pre-formed buffer patterns with specific shapes and heights facilitate subsequent bit line formation processes, making the manufacturing of wiring lines and contacts easier even with reduced design rules
Solution Approach 2:
The buffer patterns act as intermediary structures between the substrate/buried contacts and the bit line structure. These intermediate elements with varying heights and shapes simplify the direct connection process, serving as mediators that ease the manufacturing complexity of forming reliable electrical connections in highly scaled devices
Data Source
AI summary
A semiconductor device includes a device isolation layer defining a cell active area in a substrate. A plurality of buried contacts is electrically connected with the substrate and arranged in a first direction. A bit line structure extends in a second direction between adjacent buried contacts of the plurality of buried contacts. The bit line structure includes a bit line pass portion and a bit line contact portion. The bit line structure is electrically connected with the cell active area. A first buffer pattern is disposed between the substrate and the bit line pass portion. The first buffer pattern has a T-shape in a cross-section taken along the first direction.