Multi-Level Wiring Bit Line Capacitance Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with hierarchical bit line structures face issues due to differences in capacitance between main bit lines in different metal wiring layers, leading to variations in initial potentials during data read operations, which complicates the design of sense amplifiers as the operation speed increases.
Innovation Solution
A semiconductor device with a multi-level wiring structure featuring a lower-level wiring, an upper-level wiring, and an interlayer insulation film, where global bit lines are formed in two divided layers to equalize capacitance by connecting the first and second wiring layers via contact plugs, ensuring that adjacent bit lines are not juxtaposed in the same layer, thereby reducing side coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If main bit lines are provided in different metal wiring layers to reduce side coupling capacitance, then side coupling capacitance is reduced, but capacitance balance between bit lines deteriorates
Solution Approach 1:
The patent transitions from a single-layer bit line configuration to a multi-layer configuration where bit lines are distributed across different metal wiring layers. This dimensional change allows bit lines to be positioned at different heights (Z-axis) while maintaining controlled capacitance relationships through strategic layer assignment and spacing, thereby reducing side coupling capacitance while preserving capacitance balance.
Solution Approach 2:
The patent applies different wiring layer assignments to different regions of the bit line structure. Specifically, bit lines are selectively placed in second or third metal wiring layers based on their spatial position and coupling requirements, allowing local optimization of capacitance characteristics while maintaining overall balance across the entire bit line array.
2Quantity of substance
If wiring pitches are reduced to increase integration density, then integration density is improved, but side coupling capacitance increases
Solution Approach 1:
By utilizing multiple metal wiring layers stacked in the vertical dimension, the patent enables tighter horizontal spacing (reduced wiring pitches) without proportionally increasing side coupling capacitance. The vertical separation between layers provides additional isolation, allowing higher integration density while controlling parasitic capacitance effects.
3Reliability
If sense amplifier operation margins are matched across all bit lines, then operational reliability is improved, but design complexity increases due to capacitance variations
Solution Approach 1:
The patent creates equipotential conditions for all bit lines by carefully balancing their capacitance values through the multi-layer wiring structure. By ensuring that bit lines in different metal layers have matched capacitance characteristics, the patent enables sense amplifiers to operate with consistent margins across all bit lines, simplifying the design process while maintaining high reliability.
Data Source
AI summary
Disclosed herein is a semiconductor device including a multi-level wiring structure that includes a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level and upper-level wirings. The device further includes a plurality of bit lines for a plurality of memory cells, and each of the bit lines includes a first portion that is formed as the lower-level wiring and a second portion that is electrically connected in series to the first portion and formed as the upper-level wiring.