Bit Line Capacitor Adjustment for FRAM-DRAM Mode Switching
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Solution Overview
Problem
Ferroelectric memory devices face limitations in achieving high-speed operation due to the need for a large Bit Line (BL) capacitor for FRAM mode and a small BL capacitor for DRAM mode, which restricts speed improvement and leads to characteristic degradation over time.
Innovation Solution
A ferroelectric memory device with a load capacitor adjustment cell that allows for separate capacitor settings between DRAM and FRAM modes, enabling a small capacitor load for high-speed DRAM operation and secure capacitor load for FRAM mode, using a load capacitor adjustment transistor connected to the bit line control line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large BL capacitor is used for FRAM mode operation, then data holding capability during power OFF period is improved, but operation speed deteriorates
Solution Approach 1:
The patent applies dynamics by making the bit line capacitor value changeable between two states: a first capacitor value (CL1) for FRAM mode during power OFF period, and a second capacitor value (CL2) for DRAM mode during normal operation. The capacitor value is dynamically switched based on the operational mode, allowing the system to optimize between data holding capability and operation speed根据不同的工作模式
Solution Approach 2:
The patent changes the physical parameter of capacitor value to resolve the contradiction. By switching between CL1 (larger value) and CL2 (smaller value), the system adapts the electrical characteristics to match the required operational mode, enabling both reliable data holding and high-speed operation at different times
2Speed
If a small BL capacitor is used for DRAM mode operation, then operation speed is improved, but data holding capability during power OFF period deteriorates
Solution Approach 1:
The system dynamically switches the capacitor value to CL2 during normal DRAM operation to enable high-speed access, and switches to CL1 during power OFF period to ensure data holding capability. This dynamic adaptation resolves the contradiction between speed and reliability
Solution Approach 2:
The capacitor value undergoes periodic switching between CL1 and CL2 based on the operational phase: using CL2 for normal high-speed operations and switching to CL1 during power OFF periods for data preservation. This periodic parameter change allows the system to optimize performance for each operational phase
3Reliability
If FRAM mode is used for non-volatile data storage, then data retention during power OFF period is improved, but the number of polarization inversion cycles is limited
Solution Approach 1:
The system dynamically selects the operational mode based on requirements: using FRAM mode with larger capacitor CL1 during power OFF period for data retention, and switching to DRAM mode with smaller capacitor CL2 during normal operation to reduce polarization inversion cycles and extend device lifespan
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed operation comparable to SRAM, reduces data restoring time during power cutoff, and suppresses characteristic degradation by minimizing polarization inversion, improving endurance and operational efficiency.
Implementation Method 1
by using hysteresis characteristic which a ferroelectric capacitor has
Implementation Method 2
performing a Dynamic Random Access Memory (DRAM) mode operation for holding data with quantity of electrically charged up charges, and performing an FRAM mode operation for non-volatilizing data using the hysteresis characteristic
Data Source
AI summary
By separately setting a capacitor on BL depending on whether the mode is a DRAM mode or an FRAM mode, it is compatible with improvement in a speed by BL capacitor reduction in the DRAM mode and a sufficient BL capacitance in the FRAM mode.A ferroelectric memory device includes: a plurality of bit lines BL disposed in a column direction; a plurality of word lines WL disposed in a row direction; a plurality of plate lines PL and a bit line capacitor control signal BLC; a ferroelectric memory cell (32) disposed at an intersection of the plurality of bit lines BL, the plurality of word lines WL, and the plurality of plate lines PL, and composed of a ferroelectric capacitor CF and a memory cell transistor QM; and a load capacitor adjustment cell (34) disposed at an intersection of the plurality of bit lines BL and the bit line capacitor control signal BLC, and composed of a load capacitor CL and a load capacitor adjustment transistor QL.