Bit Line Charging Circuit for 3D NAND Programming Inhibit
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Solution Overview
Problem
In flash memory devices, particularly in 3D NAND architecture, the programming time (tPROG) is prolonged due to channel leakage and program disturb caused by low bit line (BL) voltages, leading to unstable programming and increased time for non-targeted memory cells to reach the intended programmed state.
Innovation Solution
Implementing a fast BL charging method using a high-voltage source higher than VCC, coupled with a BL monitor circuit to maintain a high inhibit voltage on unselected BLs, thereby reducing programming time and preventing unintended programming of non-target memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-voltage source higher than VCC is used to charge the bit line, then programming time is reduced and channel leakage is prevented, but device complexity increases due to additional charging circuitry
Solution Approach 1:
A dedicated bit line charging circuit is introduced as an intermediary component between the high-voltage source and the bit line. This charging circuit selectively applies high voltage only to unselected bit lines (BL_inhibit) during programming operations, preventing channel leakage and program disturb without requiring modification to the entire memory array or control logic.
Solution Approach 2:
The high voltage charging is applied locally and selectively only to unselected bit lines that require inhibition, rather than uniformly to all bit lines. The charging circuit monitors bit line voltage and applies high voltage only where and when needed, optimizing programming speed while minimizing impact on selected bit lines and reducing overall system complexity.
2Reliability
If high voltage is applied to unselected bit lines to prevent program disturb, then programming stability is improved, but energy consumption increases
Solution Approach 1:
The bit line charging circuit operates periodically rather than continuously. It monitors the voltage on unselected bit lines and applies high voltage only when needed to maintain the inhibit voltage level. This periodic charging approach ensures programming stability by preventing channel leakage only when necessary, rather than continuously consuming energy to maintain high voltage on all unselected bit lines throughout the entire programming operation.
Data Source
AI summary
Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL.