Bit Line Charging Circuit for NAND Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND flash memory devices, the high peak current flowing to the bit line during data writing and reading causes voltage instability and noise, leading to operational unreliability and hindered high-speed operation.
Innovation Solution
A nonvolatile semiconductor storage device configuration that includes a memory string, bit line, sense amplifier, and charging circuits with different current supply capacities to manage the voltage applied to the bit line, using a BLC driver to switch between currents and maintain stable operation while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high peak current is applied to the bit line to enable high-speed operation, then operation speed is improved, but voltage instability and noise increase leading to operational unreliability
Solution Approach 1:
The bit line is precharged to a predetermined voltage level before data writing or reading operations. This preliminary charging action prepares the bit line to rapidly accept additional charge current during the actual operation, enabling high-speed performance without requiring excessively high peak currents that would cause noise and voltage instability
Solution Approach 2:
The charging circuit dynamically switches between different current levels based on operational phase: using a first (lower) current during precharging and a second (higher) current during actual data operations. This dynamic current adjustment enables high-speed operation when needed while maintaining voltage stability during preparatory phases, resolving the contradiction between speed and reliability
2Speed
If high peak current flows to the bit line to charge it rapidly, then charging speed is improved, but power consumption increases
Solution Approach 1:
The charging operation is divided into periodic phases: a precharging phase using lower current, followed by a data operation phase using higher current. This periodic switching between current levels achieves rapid bit line charging when required while reducing overall power consumption by using lower current during the precharging period
Solution Approach 2:
By precharging the bit line to the required voltage level before data operations, the system eliminates the need to continuously apply high current. The preliminary charging action prepares the bit line in advance, allowing high-speed data operations with reduced peak current requirements and lower overall power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration inhibits power consumption and prevents bit line charge delay, maintaining stable operation reliability by managing peak currents and ensuring rapid bit line charging.
Implementation Method 1
a first charging circuit having a first current supply capacity and transferring a first current to a gate of the first MOS transistor; a second charging circuit having a second current supply capacity higher than the first current supply capacity and transferring a second current larger than the first current to the gate of the first MOS transistor
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a memory string, a bit line, a sense simplifier, a first MOS, a first charging-circuit, a second-charging circuit, and a controller. The memory string includes memory cells. The bit line is connected to the memory cell. The sense amplifier applies a voltage to the bit line. The first MOS is electrically connected between the sense amplifier and bit line. The first charging circuit has a first current supply capacity and transfers a first current. The second charging-circuit has a second current supply capacity. The controller controls a first timing to switch from the first current to the second current.