Bit Line Charging Circuit with Variable Driving Capability
Solution Overview
Problem
Existing semiconductor storage devices face challenges in reducing circuit area and peak current while maintaining power efficiency, particularly during bit line charging operations in NAND flash memory systems.
Innovation Solution
A voltage generating circuit is introduced that uses a first internal power supply voltage generated from an external power supply voltage, with a second circuit generating a charging voltage having different driving capabilities to charge the bit line, allowing for selective switching between weak and strong driving capabilities to minimize peak current and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a pre-charging circuit is arranged between blocks to shorten pre-charging time of the bit lines, then the charging speed is improved, but the circuit area increases
Solution Approach 1:
The patent combines the pre-charging function with the existing page buffer circuit by sharing the bit line connection node, eliminating the need for separate pre-charging circuits between blocks. This merging approach maintains fast charging capability while reducing overall circuit area.
Solution Approach 2:
The page buffer circuit is designed to perform multiple functions: it serves as both the readout buffer and the pre-charging circuit. The same transistors and nodes used for data readout are also utilized for pre-charging the bit line, making the circuit multi-functional and avoiding additional area consumption.
2Adaptability or versatility
If the bit line capacitance is increased along with increase of page number, then more pages can be read, but the time required to charge and discharge the bit line becomes longer
Solution Approach 1:
The patent implements preliminary pre-charging of the bit line before the actual read operation. By pre-charging the bit line to the appropriate voltage level beforehand, the subsequent charging time during the read operation is significantly reduced, allowing faster access even as page number and capacitance increase.
3Speed
If high voltage is used for pre-charging the bit line, then the charging speed is improved, but power consumption increases
Solution Approach 1:
The patent employs a two-stage periodic charging approach: first pre-charging to an intermediate voltage level, then completing the charge to the final voltage level. This periodic action allows the bit line to be charged efficiently without requiring sustained high voltage, thereby reducing overall power consumption while maintaining charging speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power inefficiencies and peak current during bit line charging, while minimizing the circuit area required for charging, thereby enhancing overall performance and efficiency.
Implementation Method 1
a first circuit generating a first internal power supply voltage by using an external power supply voltage and a second circuit generating a charging voltage at an output node for charging a bit line by using the first internal power supply voltage
Data Source
AI summary
A voltage generating circuit, a semiconductor storage device, and a bit line charging method thereof are provided. The voltage generating circuit includes: an INTVDD generating circuit for generating an internal power supply voltage INTVDD from an external power supply voltage EXVDD; a VDD_V1 generating circuit for generating an internal power supply voltage VDD_V1 from the external power supply voltage EXVDD; and a V1_driving circuit generating a charging voltage for charging the bit line at an output node by using the internal power supply voltage VDD_V1. The V1_driving circuit may generate voltages V1 having different driving capability. The V1_driving circuit charges the bit line with the voltage V1 having a weak driving capability during a first charging period of the bit line and charges the bit line with the voltage V1 having a strong driving capability during a second charging period.