Bit Line Clamping Circuit Without a Bandgap Buffer
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Solution Overview
Problem
Integrated circuit memory devices face limitations in size and speed due to the area and setup time requirements of bandgap buffers used for providing stable bit line clamping voltage, necessitating a more efficient bit line voltage generating circuit.
Innovation Solution
An unbalanced operational amplifier with a compensation current is used in the bit line voltage generating circuit, directly receiving a bandgap reference voltage to generate a stable clamping voltage independent of Process-Voltage-Temperature (PVT) effects, eliminating the need for a bandgap buffer and reducing memory area and setup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a bandgap buffer is used to convert bandgap reference voltage to generate bit line clamping voltage, then voltage stability is improved, but memory area increases and setup time increases
Solution Approach 1:
The patent extracts and eliminates the bandgap buffer component from the voltage generating circuit. By directly coupling the bit line voltage generating circuit to the bandgap reference system, the unnecessary intermediate buffer is removed, thereby reducing memory area while maintaining voltage stability through direct reference voltage acquisition.
Solution Approach 2:
The patent merges the bandgap reference system directly with the bit line voltage generating circuit by removing the bandgap buffer. This consolidation reduces the overall circuit area and simplifies the voltage generation path while maintaining stable operation through direct reference voltage supply.
2Stability of the object's composition
If a bandgap buffer is used to convert bandgap reference voltage to generate bit line clamping voltage, then voltage stability is improved, but setup time increases
Solution Approach 1:
The patent removes the bandgap buffer from the voltage generation path, eliminating the additional setup time required for buffer operation. The direct coupling between the bandgap reference system and bit line voltage generating circuit reduces the number of signal processing stages, thereby decreasing setup time while maintaining voltage stability.
Solution Approach 2:
The patent skips the intermediate buffer stage in the voltage conversion process. By directly transmitting the bandgap reference voltage to the bit line voltage generating circuit, the signal path is shortened and setup time is reduced while the voltage stability is preserved through direct reference voltage acquisition.
3Area of moving object
If memory device size is reduced, then integration density is improved, but voltage stability may deteriorate
Solution Approach 1:
The patent extracts and removes the bandgap buffer component that occupied significant area. By eliminating this intermediate component and establishing direct coupling between the reference system and voltage generating circuit, the patent achieves area reduction without compromising voltage stability.
Solution Approach 2:
The patent changes the circuit configuration parameter from using an intermediate buffer to direct coupling. This parameter change reduces the circuit area while maintaining voltage stability by directly acquiring the reference voltage, thereby achieving better integration density without sacrificing performance.
Data Source
AI summary
Systems, methods, circuits, and apparatus including computer-readable mediums for managing bit line voltage generating circuits in memory devices are provided. An example bit line voltage generating circuit is configured to provide a stable clamping voltage to at least one bit line connecting memory cells in the memory device. The bit line voltage generating circuit includes an operational amplifier configured to receive a reference voltage, a feedback voltage, and a compensation current and output an output voltage, and an output transistor configured to provide a terminal voltage as the feedback voltage and the output voltage as a target voltage that is associated with the clamping voltage. The operational amplifier is configured to be unbalanced such that the terminal voltage is smaller than the reference voltage, and the compensation current is configured to compensate the operational amplifier such that the clamping voltage is substantially constant and independent from PVT (Process-Voltage-Temperature) effect.