Bit Line Support Structure to Prevent Collapse in Memory Arrays

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Solution Overview

Problem

The fragility of bit line structures in semiconductor memory devices, due to their small critical size and high height, leads to frequent torsion, inclination, and collapse during formation, affecting electrical performance and signal transmission.

Innovation Solution

A method involving the sequential deposition of conductive and dielectric material layers on a substrate, with a supporting layer formed to create pattern structures that support the bit lines, ensuring structural integrity and stability during etching processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the critical size of the bit line is reduced and the height is increased to meet integration requirements, then the distribution density and integration of the semiconductor device are improved, but the structural strength of the bit line deteriorates, causing frequent torsion, inclination, and collapse

Engineering Contradiction:
Improvedistribution density of bit linesVSAvoidstructural strength of bit line
Core Design Contradiction:
ProductivityVSStrength

Solution Approach 1:

The patent applies local quality by forming a supporting layer with supporting pattern structures at specific locations beneath the bit line structures. These supporting patterns are strategically positioned to provide localized reinforcement where the bit lines are most vulnerable, rather than uniformly thickening the entire bit line structure. This allows the bit lines to maintain their reduced critical dimensions for high density while gaining structural support where needed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs composite materials by combining the bit line conductive material with a supporting layer made of dielectric material containing suspended particles. This composite structure integrates both the electrical function (conductive bit line) and the mechanical support function (dielectric supporting layer with particles) into a unified structure, allowing the bit line to maintain structural integrity without increasing its critical dimensions.

Inventive Principle:
Principle #40Composite materials

2Manufacturing precision

If multiple etching and wet cleaning processes are used to obtain the target bit line structure, then the manufacturing precision of the bit line is improved, but the complexity of the manufacturing process increases

Engineering Contradiction:
Improveprecision of bit line structureVSAvoidcomplexity of manufacturing process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-forming the supporting layer with supporting pattern structures before creating the bit line structures. This supporting layer is prepared in advance to provide structural reinforcement during subsequent etching and manufacturing processes, eliminating the need for multiple iterative etching and cleaning steps to achieve the desired bit line structure.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The supporting layer acts as an intermediary element between the substrate and the bit line structures. It mediates the mechanical stresses and provides structural support during the manufacturing process, allowing the bit lines to be formed with high precision without requiring complex multiple etching and wet cleaning processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11929282B2Method for preparing semiconductor structure and semiconductor structure
Publication Date: 2024.03.12 CHANGXIN MEMORY TECH INC
  • US11929282B2 patent drawing
  • US11929282B2 patent drawing
  • US11929282B2 patent drawing

AI summary

The method for preparing the semiconductor structure includes: providing a substrate; successively arranging a first conductive material layer, a barrier material layer, a second conductive material layer and a first dielectric material layer on the substrate stacked onto one another; forming a supporting layer on the first dielectric material layer, in which the supporting layer includes a plurality of supporting pattern structures spaced apart from each other, and a first trench is provided between two adjacent supporting pattern structures; forming a second dielectric layer, in which the second dielectric layer fills the first trench; etching the second dielectric layer, the first dielectric material layer, the second conductive material layer, the barrier material layer and the first conductive material layer to form a bit line array; and forming a bit line protective layer.