Bit Line Contact Connection Layout for Dense Memory Patterning

Solution Overview

Problem

The challenge of highly integrating semiconductor devices is exacerbated by the need for advanced exposure techniques to form fine patterns, making it difficult to achieve high integration density without increasing manufacturing complexity and cost.

Innovation Solution

A semiconductor memory device design featuring active patterns, bit line contacts, separation insulating patterns, and connection patterns arranged in specific directions, along with a manufacturing method that includes forming device isolation patterns, recess regions, and filling these with insulating and connection lines to enhance integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If advanced exposure techniques are used to form fine patterns, then pattern precision is improved, but manufacturing complexity and cost increase

Engineering Contradiction:

Improvepattern precisionVSAvoidmanufacturing complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The connection structure is segmented into multiple functional components: bit line contacts, separation insulating patterns, intermediate insulating patterns, and connection patterns. This segmentation allows each component to be formed with standard exposure techniques while achieving the overall fine pattern effect through their combined arrangement.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional pattern formation to three-dimensional structured arrangement by stacking insulating patterns and connection patterns in vertical layers. This dimensional approach enables fine effective patterns while using coarser individual pattern dimensions that can be formed with standard exposure techniques.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If advanced exposure techniques are used to form fine patterns, then pattern precision is improved, but manufacturing cost increases

Engineering Contradiction:

Improvepattern precisionVSAvoidmanufacturing cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The connection structure is segmented into multiple functional components: bit line contacts, separation insulating patterns, intermediate insulating patterns, and connection patterns. This segmentation allows each component to be formed with standard exposure techniques while achieving the overall fine pattern effect through their combined arrangement.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The insulating patterns serve multiple functions: electrical isolation between bit lines, structural support for connection patterns, and definition of active regions. This multi-functionality reduces the need for additional specialized components that would increase manufacturing complexity and cost.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If integration density is increased, then device functionality is improved, but manufacturing difficulty increases

Engineering Contradiction:

Improveintegration densityVSAvoidmanufacturing difficulty

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into the connection patterns structure: electrical connection, mechanical support, and isolation boundary definition. This consolidation achieves high integration density by eliminating redundant components and processes while maintaining manufacturability through standardized fabrication techniques.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from two-dimensional pattern formation to three-dimensional structured arrangement by stacking insulating patterns and connection patterns in vertical layers. This dimensional approach enables fine effective patterns while using coarser individual pattern dimensions that can be formed with standard exposure techniques.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12453085B2Semiconductor memory device having connection pattern between the bit line contact and the separation insulating pattern

Publication Date: 2025.10.21 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor memory device includes active patterns spaced apart from each other in first and second directions intersecting each other, each active pattern having a central portion, a first end portion, and a second end portion, bit line contacts disposed on the central portions and spaced apart from each other in the first and second directions, separation insulating patterns, each of which is disposed between the bit line contacts adjacent to each other in the first and second directions, intermediate insulating patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the first direction, and connection patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the second direction.