Bit Line Contact Formation in DRAM Manufacturing
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Solution Overview
Problem
During the manufacturing of dynamic random access memory (DRAM), voids or seams often form in bit line contacts, leading to performance degradation due to uneven filling and reduced charge transmission capabilities.
Innovation Solution
A manufacturing method that involves forming a first etched hole and bit line contact hole, removing the first mask layer and conductive layer around the bit line contact hole, and ensuring the bit line contact is flush with the barrier layer, thereby reducing the formation height and avoiding voids or seams, improving charge transmission and memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the bit line contact is formed with conventional manufacturing methods, then the contact structure is simple, but voids or seams form within the bit line contact resulting in performance degradation
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming the first etched hole through mask layer and conductive layer, then forming the bit line contact hole through the substrate, and finally filling to create the bit line contact. This segmentation allows each stage to be optimized independently, ensuring proper filling without voids or seams while maintaining manageable process complexity.
Solution Approach 2:
The first mask layer and first conductive layer are formed and patterned before the bit line contact formation. This preliminary action creates a structured template that guides the subsequent etching and filling processes, ensuring that the bit line contact is formed with proper geometry and without defects, thereby improving contact quality without excessive complexity.
2Reliability
If the bit line contact formation height is reduced, then voids or seams are avoided improving charge transmission, but the manufacturing process becomes more complex
Solution Approach 1:
The method applies different treatment to different regions: the first mask layer and first conductive layer are removed in the core region around the bit line contact hole, but retained in the peripheral region. This local quality approach ensures proper contact formation and eliminates voids in the critical contact area while maintaining overall process feasibility.
Solution Approach 2:
The first mask layer and first conductive layer are extracted (removed) from the core region surrounding the bit line contact hole. This extraction eliminates the sources of voids and seams by removing excess material that would interfere with proper contact filling, thereby improving charge transmission capability.
Data Source
AI summary
The present application provides a manufacturing method of a memory. The manufacturing method includes: providing a substrate, where the substrate includes a core region and a peripheral region, and a first barrier layer is provided in the core region; laminating and forming a first conductive layer and a first mask layer on the substrate in sequence; etching the first mask layer, the first conductive layer, and the first barrier layer in the core region, to form a first etched hole; etching the substrate along the first etched hole, to form a bit line contact hole; removing the first mask layer and the first conductive layer in the core region and located around the bit line contact hole; and forming a bit line contact in the bit line contact hole.