Semiconductor Bit Line Contact Etching for Lower RC Delay
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Solution Overview
Problem
The challenge of reducing leakage and improving process yield in highly integrated semiconductor structures is exacerbated by shrinking sizes and close distances, leading to increased capacitance and RC-delay effects due to etching processes that inadvertently shorten spacer-gate distances.
Innovation Solution
A two-step etching process is employed, where a second dielectric layer with higher selectivity is used to form openings, protecting spacers and maintaining consistent distances, followed by forming bit line contacts with straight profiles to reduce capacitance and RC-delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional single-step etching process is used to form openings, then the manufacturing process is simple and fast, but the etching process inadvertently shortens spacer-gate distances leading to increased capacitance and leakage
Solution Approach 1:
The etching process is divided into two distinct steps: first etching the second dielectric layer to form initial openings, then etching the first dielectric layer to form final openings with straight profiles. This segmentation allows each etching step to be optimized independently, preventing the inadvertent shortening of spacer-gate distances while maintaining manufacturing efficiency.
Solution Approach 2:
The second dielectric layer is deposited and etched first to create preliminary openings that serve as guides for the subsequent etching of the first dielectric layer. This preliminary action ensures that the final openings maintain straight profiles and consistent spacer-gate distances, preventing capacitance increase before the actual bit line contact formation.
2Productivity
If the pitch between semiconductor structures is shortened to increase integration, then device density improves, but components become prone to leakage due to too close distances
Solution Approach 1:
The two-step etching process segments the opening formation into controlled stages, ensuring that even when pitch is reduced for higher integration, the bit line contacts maintain straight profiles and proper spacing relationships. This prevents leakage issues that would otherwise arise from closely spaced structures.
3Reliability
If bit line contacts have non-straight profiles due to etching, then capacitance increases and RC-delay effects worsen, but achieving straight profiles requires complex multi-step processes
Solution Approach 1:
The etching process is segmented into two steps using different dielectric layers with selective etching characteristics. The first dielectric layer is etched to form straight-walled openings while the second dielectric layer provides a protective cushion, achieving straight bit line contact profiles without requiring additional complex process steps.
Solution Approach 2:
The second dielectric layer acts as an intermediary protective layer during the etching process. It is etched first to create openings, then serves as a barrier that prevents over-etching and maintains straight profiles of the bit line contacts, simplifying the overall process while achieving the desired geometric precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method maintains consistent spacer-gate distances, reducing capacitance and improving process yield by ensuring straight bit line contact profiles, thereby minimizing RC-delay effects.
Implementation Method 1
an etching selectivity of the second dielectric layer is greater than an etching selectivity of the first dielectric layer
Implementation Method 2
an etching selectivity of the first dielectric layer is greater than an etching selectivity of each of the two spacers of the gate structure
Implementation Method 3
The first dielectric layer is planarized, and the top surface of the first dielectric layer and the top surface of the gate structure are coplanar
Data Source
AI summary
Embodiments of this disclosure provide a semiconductor structure, including an active area disposed in a substrate, a gate structure disposed on the active area, two source/drain regions disposed in the substrate on both sides of the gate structure, two bit line contacts disposed on the both sides of the gate structure, a first dielectric layer surrounding an upper portion of the gate structure and a second dielectric layer surrounding an upper portion of each of the two bit line contacts. Each of the two bit line contacts directly contacts a portion of each of the two source/drain regions. Additionally, a method of manufacturing a semiconductor structure is also provided in this disclosure.