Island Bit-Line Contact Pads for Flexible 3D Memory Routing
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Solution Overview
Problem
Current semiconductor devices face limitations in the degree of freedom for line connections, which restricts the integration and efficiency of three-dimensional memory cell arrays.
Innovation Solution
The semiconductor device incorporates a bit-line contact pad with an island shape, electrically coupling bit lines to lower connection structures through a series of connection patterns, allowing for improved connectivity and flexibility in line connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional line connection structures are used in 3D semiconductor devices, then manufacturing process is simpler, but the degree of freedom in line connections is limited
Solution Approach 1:
The connection structure is divided into multiple discrete components: connection patterns formed in lower layers, bit-line contact pads formed in intermediate layers, and bit lines formed in upper layers. This segmentation allows each component to be independently optimized and connected through vertical vias, thereby increasing the degree of freedom in line connections while managing complexity through modular construction
Solution Approach 2:
The patent transitions from planar 2D connections to 3D vertical connections by forming connection patterns that extend in the vertical direction through multiple layers. Bit-line contact pads are positioned at different vertical levels to connect bit lines to lower connection structures, enabling three-dimensional routing flexibility that significantly increases connection freedom
2Quantity of substance
If three-dimensional memory cell arrays are implemented, then integration density is improved, but line connection flexibility is restricted
Solution Approach 1:
The patent implements nested connection structures where connection patterns are embedded within lower layers, bit-line contact pads are positioned within intermediate layers, and bit lines are formed in upper layers. This nested arrangement allows multiple connection levels to be stacked vertically, maintaining high integration density while providing flexible routing options through different vertical levels
Solution Approach 2:
Bit-line contact pads serve as intermediary elements that mediate the connection between upper-layer bit lines and lower-layer connection structures. These contact pads act as vertical vias or through-conductors that enable signal transmission across multiple layers, thereby maintaining connection flexibility within the high-density 3D memory architecture
Data Source
AI summary
A semiconductor device includes a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction. A predetermined number of the bit-line contact pads are spaced apart from each other by a predetermined distance in a first direction, when viewed along the vertical direction.