Semiconductor Bit Line Contact Formation via Side Wall Patterning
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Solution Overview
Problem
The increasing integration of semiconductor devices leads to reduced critical dimensions, making it difficult to form bit line contacts smaller than 30 nm, which can result in short-circuiting between bit line and storage node contacts due to the high aspect ratio of contacts and the need for precise mask alignment.
Innovation Solution
A method involving the formation of a line type conductive layer on a semiconductor substrate with a buried gate, where a bit line contact is formed by patterning a line rather than a contact hole, using a photo-resist pattern to expose specific regions and etching the conductive layer to prevent connection with storage node contacts, allowing for precise formation of fine critical dimension bit line contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration degree of semiconductor devices is increased, then the memory capacity and performance are improved, but the critical dimension of patterns is reduced making contact formation difficult
Solution Approach 1:
Instead of forming contact holes through the bit line (conventional approach), the patent inverts the approach by forming the bit line contact through the side wall of the bit line. This inversion allows the contact to be formed at a location that is easier to pattern with precise dimensions, avoiding the difficulties of forming sub-30nm contact holes through high-aspect-ratio structures.
Solution Approach 2:
The patent transitions from forming contacts in the vertical dimension (through-hole contacts) to forming contacts in the horizontal dimension (side-wall contacts). By moving the contact formation to the side wall of the bit line, the critical dimension is determined by the bit line width rather than the contact hole diameter, enabling better dimensional control.
2Reliability
If the contact size is reduced to prevent bridge phenomenon, then the short circuit risk is reduced, but it becomes difficult to form uniform contacts with precise dimensions
Solution Approach 1:
The patent inverts the conventional contact formation approach by creating side-wall contacts rather than through-hole contacts. This allows the contact dimensions to be defined by the bit line geometry rather than requiring direct patterning of sub-30nm contact holes, achieving both small size for bridge prevention and uniformity for reliable formation.
Solution Approach 2:
The patent uses the bit line side wall as an intermediary structure to define the contact geometry. Instead of directly patterning the contact, the contact is formed conformally on the bit line side wall, using the bit line itself as a template that ensures uniform dimensions and spacing.
3Ease of manufacture
If conventional contact formation methods are used, then the process is simple, but it is difficult to form bit line contacts smaller than 30 nm without short-circuiting
Solution Approach 1:
The patent inverts the conventional approach of forming contacts through the bit line by instead forming contacts on the bit line side wall. This inversion enables sub-30nm contact dimensions to be achieved while maintaining process simplicity, as the contact geometry is defined by the bit line structure rather than requiring complex direct patterning.
Solution Approach 2:
The patent performs preliminary formation of the bit line structure with well-defined dimensions before forming the contacts. By establishing the bit line geometry first, the subsequent contact formation can proceed with simpler processes, as the bit line side wall already provides the necessary dimensional constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the easy formation of bit line contacts with fine critical dimensions, preventing short-circuiting and allowing for precise exposure of storage node contact locations, thereby increasing the process margin and reducing the aspect ratio of bit lines.
Implementation Method 1
using a photo-resist pattern to expose specific regions and etching the conductive layer
Data Source
AI summary
A method for forming a highly integrated semiconductor device having multiplayer conductive lines is presented. The method includes the operations of forming, etching, burying and forming. The first forming operation includes forming a line-type conductive layer on a semiconductor substrate including a buried gate to expose the gate. The etching operation includes etching the conductive layer to expose at least a region between one side of an active area defined in the semiconductor substrate and an opposite side of the neighboring active area, both the active areas being arranged next to each other in a major axis direction of the gate. The burying operation includes burying a first insulating film in the etched line-type conductive layer. The second forming operation includes forming a bit line passing through the center of the active area in a direction perpendicular to the major axis direction of the gate.