Bit Line Contact Spacer Structure for Short-Circuit Prevention

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Solution Overview

Problem

As the degree of integration of semiconductor devices increases, the area occupied by patterns decreases, leading to potential short circuit defects due to conductive material remaining during contact plug formation, which existing methods fail to adequately prevent.

Innovation Solution

A semiconductor device and method involving the formation of a first spacer and a second spacer to prevent short circuits, where the second spacer is positioned between the contact plug and the first spacer, and a sacrificial spacer is used to enhance etching and gap formation, reducing the risk of dopant flow and improving etching rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the area occupied by patterns is decreased to increase degree of integration, then productivity and device density are improved, but short circuit defects occur due to conductive material remaining during contact plug formation

Engineering Contradiction:
Improvedegree of integrationVSAvoidshort circuit defect
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A spacer is formed around the contact plug before the conductive material filling process. This preliminary spacer structure prevents conductive material from shorting adjacent contact plugs during the filling process, thereby maintaining high integration while preventing short circuit defects

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spacer acts as an intermediary barrier between adjacent contact plugs. It physically separates the conductive materials during formation, preventing direct contact and short circuits while allowing the high-density layout to be maintained

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a spacer is formed to prevent short circuit defects, then reliability is improved, but device complexity increases due to additional fabrication steps

Engineering Contradiction:
Improveshort circuit preventionVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The spacer formation process is merged with the existing contact plug fabrication sequence. The spacer is formed as part of the interlayer dielectric structure, combining multiple functions into a single integrated process step rather than adding separate dedicated steps

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If etching is performed to form contact holes and gaps, then manufacturing precision is improved, but dopant flow occurs causing contamination

Engineering Contradiction:
Improvecontact hole formation precisionVSAvoiddopant flow
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The spacer structure is formed beforehand to create a physical barrier that prevents dopant flow during etching operations. This preliminary protective structure counteracts the harmful dopant migration before it can occur, while still allowing precise contact hole formation

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS12062577B2Semiconductor device and method for fabricating the same
Publication Date: 2024.08.13 SK HYNIX INC
  • US12062577B2 patent drawing
  • US12062577B2 patent drawing
  • US12062577B2 patent drawing

AI summary

A method for fabricating a semiconductor device includes forming a bit line contact hole in a substrate; forming a first spacer on a sidewall of the bit line contact hole; forming a sacrificial spacer over the first spacer; forming a first conductive material that fills the bit line contact hole over the sacrificial spacer; forming a second conductive material over the first conductive material; forming a bit line by etching the second conductive material; and forming a bit line contact plug and a gap between the bit line contact plug and the first spacer by partially etching the first conductive material and the sacrificial spacer to be aligned with the bit line.