Bit Line Contact Test Structure for Accurate Resistance Measurement

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Solution Overview

Problem

Existing semiconductor manufacturing processes face significant measurement errors when testing the contact resistance of bit line contact structures due to the large number of parallel conductive paths, which affects the accuracy of the test-key structure.

Innovation Solution

A semiconductor structure is designed with a test region that includes a semiconductor substrate with separate active regions, bit line contact structures, and wire groups. Each active region is electrically connected to two bit line contact structures, and the wire groups form conductive paths by connecting adjacent bit line contact structures, reducing the impact of external interference and measurement errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a test-key structure with multiple parallel conductive paths is used to test contact resistance, then the test coverage is improved, but the measurement precision deteriorates due to large errors

Engineering Contradiction:
Improvetest coverageVSAvoidcontact resistance measurement accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent divides the test structure into multiple separate active regions (first, second, third, and fourth active regions) with individual bit line contact structures for each region. This segmentation isolates the measurement paths, allowing contact resistance to be measured in separate, independent paths rather than through multiple parallel paths simultaneously. The segmentation principle directly resolves the measurement precision issue by eliminating the error accumulation that occurs in parallel path measurements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating distinct test regions with specific configurations optimized for contact resistance measurement. Each active region has its own dedicated bit line contact structures and wire connections, allowing the test structure to have different local characteristics tailored for accurate contact resistance measurement. This local optimization ensures that each measurement path has consistent and controlled properties, improving overall measurement precision.

Inventive Principle:
Principle #3Local quality

2Ease of operation

If multiple parallel conductive paths are used in the test structure, then the test facilitation is improved, but the reliability of measurement deteriorates due to external interference

Engineering Contradiction:
Improvetest facilitationVSAvoidmeasurement reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The test structure is segmented into multiple separate active regions, each with its own isolated conductive path. This segmentation prevents external interference from affecting multiple measurement paths simultaneously, as each path is electrically isolated. The first, second, third, and fourth active regions can be tested independently, maintaining measurement reliability while still providing comprehensive test coverage through the segmented architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces separate wire connections (first wire, second wire, third wire, fourth wire) as intermediaries that connect the bit line contact structures to the measurement equipment. These intermediary wires provide controlled and isolated electrical connections for each active region, preventing external interference from directly affecting the measurement paths. The intermediary wires act as buffers that maintain signal integrity and measurement reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12218016B2Semiconductor structure
Publication Date: 2025.02.04 CHANGXIN MEMORY TECH INC
  • US12218016B2 patent drawing
  • US12218016B2 patent drawing
  • US12218016B2 patent drawing

AI summary

A semiconductor structure is provided with a test region. In test region, the semiconductor structure includes a semiconductor substrate, a plurality of bit line contact structures arranged on semiconductor substrate and a plurality of wire groups. The semiconductor structure is provided with a plurality of separate active regions extending along a first direction. In first direction, each active region is electrically connected to two bit line contact structures. The plurality of wire groups are arranged along a second direction. Each wire group includes a plurality of wires extending along a third direction. In third direction, each of two bit line contact structures for each active region is connected to respective one of two bit line contact structures for active region adjacent to said each active region by a respective one of wires, so that two wire groups of the wire groups cooperate with each other to form a conductive path.