Bit Line Control Reduces Select Gate Transistor Disturb in Erase Operations
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Solution Overview
Problem
Select gate transistors in non-volatile memory devices experience unstable threshold voltage distribution after multiple program-erase cycles, leading to memory block failure due to channel potential gradients during erase operations.
Innovation Solution
The implementation of an erase circuit that controls the bit line and substrate voltages to maintain a channel potential gradient below a predetermined threshold, by stepping down the bit line voltage and increasing the substrate voltage in stages, while floating the bit line voltage to couple with the substrate voltage, thereby reducing electron injection into the select gate transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bit line voltage is rapidly changed during erase operations, then the erase operation speed is improved, but the channel potential gradient increases causing electron injection into select gate transistors and threshold voltage instability
Solution Approach 1:
The bit line is pre-charged to an intermediate voltage level before the main erase operation begins. This preliminary action reduces the voltage differential across the channel during the erase operation, thereby reducing the channel potential gradient and preventing electron injection into the select gate transistors while still maintaining efficient erase operation speed
Solution Approach 2:
The patent implements dynamic voltage control by adjusting the bit line voltage in stages rather than applying a fixed voltage. The bit line voltage is first set to an intermediate level, then adjusted to the final erase voltage after the channel has been pre-charged. This dynamic adjustment maintains low channel potential gradient throughout the operation while achieving complete erase functionality
2Reliability
If the channel potential gradient is reduced to prevent electron injection, then select gate transistor reliability is improved, but the erase operation efficiency may be reduced
Solution Approach 1:
The channel is pre-charged to an intermediate voltage level before the final erase voltage is applied. This preliminary charging action ensures that when the full erase voltage is eventually applied, the channel potential gradient remains controlled while still achieving effective electron hole injection for complete erasure of the memory cells
Solution Approach 2:
The erase operation is divided into multiple voltage application stages rather than a single continuous voltage application. The bit line voltage is applied in periodic steps: first to an intermediate level for pre-charging, then to the final erase level for complete erasure. This periodic voltage application maintains reliability while ensuring complete erase efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the channel potential gradient, preventing electron injection and maintaining the stability of select gate transistors, thereby extending the lifespan of memory blocks and preventing failure during read or program operations.
Implementation Method 1
the source line driver is configured to raise a voltage of the substrate in relation to a change in the voltage of the bit line controlled by the bit line driver, to charge up the memory channel to an erase voltage threshold such that a channel potential gradient of the memory channel between the bit line and the select gate transistor stays below a predetermined threshold
Data Source
AI summary
A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.