Semiconductor Memory Bit Line Arrangement for Coupling Disturbance
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Solution Overview
Problem
Conventional NAND type flash memory devices experience coupling disturbance between adjacent memory cells due to the arrangement of bit lines, which affects the reliability and operational characteristics of the device.
Innovation Solution
The bit lines in the semiconductor memory device are arranged on multiple parallel planes at different heights, with even and odd bit lines alternating in a repeating pattern, reducing coupling disturbance during programming and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit lines are arranged in even/odd/even/odd order in a single plane, then device integration is simplified, but coupling disturbance between adjacent cells increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from a single-plane bit line arrangement to a multi-plane (three-dimensional) arrangement. Specifically, even bit lines and odd bit lines are disposed on different planes, creating vertical separation that reduces capacitive coupling between adjacent cells while maintaining the even/odd ordering benefit for device integration.
2Ease of operation
If odd cells are disposed on both ends of even cells, then cell connectivity is improved, but coupling disturbance during programming increases
Solution Approach 1:
The patent resolves this contradiction by using vertical plane separation to isolate the harmful coupling effect. Odd cells remain connected to odd bit lines and even cells to even bit lines, but the even and odd bit lines are placed on different planes, thereby reducing the coupling disturbance generated during programming operations.
Solution Approach 2:
The different planes act as an intermediary spatial layer that separates the even and odd bit line systems. This physical separation in the vertical dimension reduces the electromagnetic coupling between adjacent even and odd cells while preserving the electrical connectivity needed for cell operation.
Data Source
AI summary
A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.