Bit Line Coupling in Flash Memory via Select Gates
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Solution Overview
Problem
Conventional flash memory devices experience bit-line-to-bit-line cross-coupling effects due to the lack of shielding, which affects the accuracy of program and read operations, particularly in memory devices with bit lines at different vertical levels.
Innovation Solution
The solution involves concurrently selecting alternate bit-line pairs, where each bit-line pair consists of one bit line at a first vertical level and an adjacent bit line at a second vertical level, using select gates and multiplexing circuitry to couple these bit lines to sensing devices, thereby reducing cross-coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If bit lines are located on different vertical levels without shielding, then device integration is improved, but bit-line-to-bit-line cross coupling effects increase
Solution Approach 1:
The patent introduces select gates as intermediary elements between bit lines and sensing devices. These select gates act as mediators that control and isolate bit line signals, preventing direct cross-coupling between adjacent bit lines on different vertical levels while maintaining the integrated three-dimensional structure.
Solution Approach 2:
The patent segments the bit line structure by introducing select gates that divide the continuous bit line into isolated segments. This segmentation prevents signal leakage and cross-coupling between adjacent bit lines while preserving the vertical stacking architecture for high-density integration.
2Device complexity
If conventional bit line selection is used, then device simplicity is maintained, but cross coupling effects occur
Solution Approach 1:
Select gates are introduced as intermediary control elements that manage bit line selection without significantly increasing overall device complexity. These gates provide precise control over which bit lines are active, eliminating cross-coupling effects while adding minimal structural overhead to the flash memory architecture.
3Quantity of substance
If bit lines at different vertical levels are used, then storage density is improved, but shielding is reduced leading to cross coupling
Solution Approach 1:
The select gates serve as intermediary elements that enable the use of bit lines at different vertical levels for high-density storage while preventing cross-coupling. By controlling signal flow through these intermediary gates, the patent achieves vertical stacking for increased capacity without suffering from shielding deficiencies.
Solution Approach 2:
The patent segments the vertical bit line structure into isolated sections using select gates, allowing dense vertical stacking while preventing signal interference between levels. This segmentation maintains storage density benefits without the cross-coupling problems that would otherwise result from lacking shielding.
Data Source
AI summary
The invention provides methods and apparatus. Alternate bit-line pairs of a memory device are concurrently selected. Each bit-line pair has one bit line formed at a first vertical level and one adjacent bit line formed at a second vertical level different than the first vertical level.