Bit Line Coupling Transistor Layout for Non-Volatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing non-volatile semiconductor memory devices face challenges in achieving high-speed operation while preventing high voltages from being applied to the sense amplifier circuit, which can lead to reliability issues and leakage currents during erasing operations due to the thinning gate insulating film and high voltage requirements.
Innovation Solution
The implementation of a bit line coupling circuit with a first and second bit line coupling transistor in outer and inner layout areas, respectively, where the first transistor has a longer channel length distance between the impurity diffused layer and the element isolation area, effectively isolating high voltages from the sense amplifier circuit and reducing leak currents by optimizing the layout and impurity distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate insulating film is made thinner to enable high-speed sense amplifier operations, then the operation speed is improved, but the withstand voltage capability deteriorates and leak currents increase
Solution Approach 1:
The patent applies different gate insulating film thicknesses to different functional regions: the sense amplifier circuit uses a thin gate insulating film (first thickness) for high-speed operation, while the bit line coupling transistor uses a thick gate insulating film (second thickness greater than first) for high voltage withstand capability. This local differentiation resolves the contradiction by allowing each region to be optimized for its specific function without compromising the other.
2Reliability
If a bit line coupling transistor is added to protect the sense amplifier circuit from high voltage, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent merges the bit line coupling transistor with the sense amplifier circuit layout, positioning it adjacent to and integrated with the existing circuit structures. The coupling transistor shares the same semiconductor substrate and is formed using compatible fabrication processes, allowing it to be incorporated into the existing device architecture without requiring separate processing steps or additional complex structures.
3Reliability
If the distance between the impurity diffused layer and element isolation area is increased in the outer layout area, then the leak current is reduced and withstand voltage is improved, but the area occupied by the transistor increases
Solution Approach 1:
The patent applies different structural configurations to transistors in different layout areas: transistors in the outer layout area (exposed to high voltage) have a longer distance between the impurity diffused layer and element isolation area for reduced leak current and enhanced withstand voltage, while transistors in the inner layout area use a more compact configuration. This local differentiation allows each transistor to be optimized for its specific electrical environment while minimizing overall device area.
Data Source
AI summary
A non-volatile semiconductor memory device includes a memory cell configured to allow electrical writing and erasing, a bit line configured to transmit a potential corresponding to data stored in the memory cell in a column direction, a sense amplifier circuit configured to detect a potential of the bit line, and a bit line coupling circuit coupled between the bit line and the sense amplifier circuit. The bit line coupling circuit includes a first bit line coupling transistor in an outer layout area of the bit line coupling circuit and a second bit line coupling transistor in an inner layout area of the bit line coupling circuit. The first bit line coupling transistor has a longer distance in a channel length direction or in a channel width direction between an impurity diffused layer coupled to the bit line and an element isolation area than the second bit line coupling transistor.