Bit Line Driving for NAND Flash Channel-to-Floating Gate Coupling

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Solution Overview

Problem

As memory devices become smaller, capacitive coupling effects during programming become more problematic, leading to increased programming speed and widened threshold voltage distributions in non-volatile semiconductor memory devices like NAND flash memory, which affects the accuracy and efficiency of data storage.

Innovation Solution

The implementation of sensing circuits and programming techniques that optimize bit line driving and floating to compensate for channel-to-floating gate capacitive coupling, allowing for adaptive slowing of programming speed and precise control of threshold voltage distributions without additional verify operations, by determining the need for compensation based on bit line-to-bit line coupling and channel potential.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If memory devices are scaled down to reduce size, then device dimensions are improved, but capacitive coupling effects increase causing programming speed to increase uncontrollably and threshold voltage distributions to widen

Engineering Contradiction:

Improvememory device sizeVSAvoidthreshold voltage distribution precision

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies preliminary anti-action by detecting capacitive coupling effects before they cause excessive programming speed increases, and applying compensating voltages to counteract the coupling effects. The system monitors threshold voltage changes during programming and applies reverse voltages to offset the capacitive coupling, preventing the harmful effect from occurring in the first place.

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

The patent changes electrical parameters (voltages applied to bit lines and word lines) dynamically during the programming process to compensate for capacitive coupling effects. By adjusting voltage levels and timing based on detected coupling conditions, the system maintains precise control over threshold voltage distributions despite device scaling.

Inventive Principle:

Principle #35Parameter changes

2Volume of moving object

If memory devices are scaled down, then device dimensions are improved, but programming speed becomes uncontrollably fast affecting verification accuracy

Engineering Contradiction:

Improvememory device sizeVSAvoidverification accuracy

Core Design Contradiction:

Volume of moving objectVSMeasurement precision

Solution Approach 1:

The patent implements feedback by continuously monitoring threshold voltage changes during programming and using this information to adjust subsequent programming pulses. The system measures the actual voltage distribution, compares it to target values, and modifies programming parameters in real-time to maintain verification accuracy despite accelerated programming speeds from capacitive coupling.

Inventive Principle:

Principle #23Feedback

3Volume of moving object

If conventional programming is used with scaled devices, then device size is reduced, but additional verify operations are needed increasing programming time

Engineering Contradiction:

Improvememory device sizeVSAvoidprogramming time

Core Design Contradiction:

Volume of moving objectVSLoss of time

Solution Approach 1:

The patent converts the harmful capacitive coupling effect into a beneficial feature by using the coupled voltage to extend the effective programming window. Instead of fighting the coupling effects, the system utilizes them to maintain programming effectiveness without requiring additional verify operations, thereby reducing total programming time despite device scaling.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces capacitive coupling effects, maintaining intended programming speeds and achieving tighter threshold voltage distributions, thereby enhancing the accuracy and efficiency of data storage in non-volatile memory devices.

Implementation Method 1

capacitive coupling effects become more problematic during programming

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Implementation Method 2

electrons from the channel of a storage element to be injected into the floating gate

Methodology Applied

Scientific EffectElectron injection: Electron Beam

Data Source

PatentEP2504839B1Programming memory with direct bit line driving to reduce channel-to-floating gate coupling

Publication Date: 2016.01.06 SANDISK TECHNOLOGIES LLC

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AI summary

During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines. Dedicated power supplies can be used to provide the step up to avoid a risk that the unselected bit lines begin floating due to pre-charging of other bit lines The selected bit lines are coupled higher as a function of their proximity to unselected bit lines, and in preparation for applying a program pulse. Coupling may be used for slow and fast programming modes. A dedicated power supply can be provided for driving slow programming mode bit lines at a level which provides coupling compensation.