Bit Line Contact Structure With Dual Spacers for Overlay Margin
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Solution Overview
Problem
The manufacturing of semiconductor devices with high aspect ratio contact holes is challenging due to misalignment issues, leading to defects that can deteriorate the electrical characteristics or render the devices defective.
Innovation Solution
A semiconductor device design featuring a stacked structure of bit line and bit line hard mask with specific spacer structures, including a first spacer with a higher dielectric constant and a second spacer with a lower dielectric constant, to improve alignment and reduce parasitic capacitance, along with a method for fabricating the device that includes forming contact structures and spacer layers to enhance contact resistance and overlay margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact plug size is decreased to increase integration density, then device integration density is improved, but aspect ratio of contact holes increases leading to misalignment and manufacturing defects
Solution Approach 1:
The contact hole formation process is segmented into multiple etching stages with separate alignment procedures. The etch mask pattern is formed first, then a first alignment procedure aligns the etch mask with a first reference pattern, followed by a second alignment procedure that aligns with a second reference pattern. This segmentation allows each alignment step to be optimized independently, maintaining precision even as contact hole size decreases for higher integration density.
Solution Approach 2:
The etch mask pattern is formed in advance before the actual contact hole etching process. This preliminary action includes forming the etch mask with specific thickness and pattern dimensions, then performing alignment procedures beforehand to ensure precise positioning. By preparing the etch mask and performing alignments preliminarily, the subsequent etching process can proceed with high precision despite the small contact hole dimensions required for increased integration density.
2Productivity
If contact hole aspect ratio is increased to maintain contact plug size at higher integration, then integration density is improved, but misalignment occurs during etching process
Solution Approach 1:
The etch mask serves as an intermediary element that mediates between the alignment references and the final contact hole formation. The etch mask is formed with controlled thickness and pattern, then used as the reference for alignment procedures. This intermediary structure allows precise alignment to be achieved even when the final contact holes have high aspect ratios, because the alignment is performed on the more robust etch mask structure rather than directly on the narrow contact holes.
Solution Approach 2:
The alignment process uses parameter changes by performing multiple alignment procedures with different reference patterns. The first alignment procedure uses a first reference pattern, then the second alignment procedure uses a second reference pattern. By changing the reference parameters and performing sequential alignments, the system achieves high measurement precision for the etching process despite the high aspect ratio of the contact holes that would be difficult to align directly.
3Length of stationary object
If contact hole size is reduced for higher integration, then device size is decreased, but contact resistance increases and electrical characteristics deteriorate
Solution Approach 1:
The contact structure uses a nested configuration where the contact hole is formed within the semiconductor device structure, and the etch mask is nested within the device layers during the formation process. This nesting allows the contact holes to be precisely positioned within the high-density device architecture while maintaining adequate dimensions for acceptable contact resistance. The sequential alignment procedures ensure that even nested contact structures maintain proper electrical characteristics.
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; a plurality of bit line structures spaced apart from each other over the semiconductor substrate and each including a stacked structure of a bit line and a bit line hard mask; a contact pad positioned over the semiconductor substrate between the neighboring bit line structures; a contact structure including a stacked structure of a first contact formed over the contact pad and a second contact having a greater line width than the first contact; a first spacer structure interposed between the first contact and each of the bit line structures; and a second spacer structure interposed between the second contact and each of the bit line structures and having a smaller dielectric constant than the first spacer structure.