Bit Line Equalizer Layout for Faster Memory Precharge
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Solution Overview
Problem
Conventional semiconductor memory devices with shared bit line sense amplifiers (BLSA) suffer from inefficiencies in bit line equalization, leading to increased precharge time and current leakage due to the lack of bit line equalizers within the cell arrays, especially in large-capacity memory devices.
Innovation Solution
Incorporating bit line equalizers directly into the cell arrays, connected through signal lines, allowing each bit line pair to be equalized independently, and sharing bit line sense amplifiers between neighboring cell arrays to receive respective equalization signals, thereby reducing the reliance on BLSA units for equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit line equalizers are only included in BLSA units, then device complexity is reduced, but precharge time increases and equalization efficiency decreases
Solution Approach 1:
The patent divides the bit line equalization function into two segments: cell array bit line equalizers (equalizing bit lines within the same cell array) and BLSA unit bit line equalizers (equalizing bit lines in neighboring cell arrays). This segmentation allows localized equalization to occur faster, reducing precharge time while maintaining manageable device complexity through functional distribution.
2Productivity
If bit line equalizers are added to cell arrays, then equalization efficiency improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by placing bit line equalizers specifically where they are most needed - within cell arrays for local equalization. This allows high equalization efficiency for local bit line pairs while avoiding unnecessary equalization components in other areas, thus improving productivity without proportionally increasing overall device complexity.
Solution Approach 2:
The BLSA unit is designed to serve multiple functions: it acts as a sense amplifier for reading data and includes a bit line equalizer for equalizing bit lines in neighboring cell arrays. This multi-functionality allows the system to achieve high equalization efficiency without adding dedicated equalization hardware everywhere, thereby controlling device complexity.
3Device complexity
If BLSA units are shared between cell arrays, then device complexity is reduced, but current leakage increases due to longer precharge time
Solution Approach 1:
The patent implements preliminary action by performing bit line equalization within the cell array before the shared BLSA unit needs to precharge the bit lines. The cell array bit line equalizer equalizes the bit line voltages in advance, so when the precharge operation begins, the bit lines are already at equalized voltage levels, reducing the precharge time and minimizing current leakage.
Data Source
AI summary
A semiconductor memory device includes at least one cell array and first and second bit line sense amplifying units. A cell array includes a plurality of bit line pairs and a plurality of bit line equalizers connected to each other through a signal line. Each bit line equalizer equalizes a corresponding bit line pair. The first and the second bit line sense amplifying units are alternately connected to the bit line pairs and receive respective bit line equalization signals.