Bit Line Equalizing Control Circuit for RAS Precharge Optimization
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face challenges in reducing the RAS precharge time (tRP), as the time required to equalize bit lines and complement bit lines after a precharge command is input is not efficiently managed, limiting the manufacturing of high-speed memory devices.
Innovation Solution
A bit line equalizing control circuit that includes a control signal generating unit to delay the enabling of the bit line equalizing signal, a bit line equalizing selecting unit to generate detection signals based on mat select signals and control signals, and a driver to generate the bit line equalizing signal, allowing for delayed release of equalization, thereby extending the time period and enhancing the RAS precharge time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bit line equalizing signal is enabled immediately after a precharge command is input, then the bit line equalization process starts promptly, but the RAS precharge time (tRP) is extended, limiting high-speed memory performance
Solution Approach 1:
The patent applies preliminary action by detecting the mat selection state before the precharge operation completes, and preparing the bit line equalizing signal timing in advance. The control circuit determines whether bit line equalization is needed based on the mat select signals, and schedules the equalization timing to occur at the optimal moment during the precharge sequence, thereby reducing the overall RAS precharge time without compromising signal integrity.
2Productivity
If the bit line equalizing signal is delayed to extend RAS precharge time, then high-speed memory performance is improved, but the bit line equalization process is postponed, potentially affecting signal stability
Solution Approach 1:
The patent changes the timing parameter of the bit line equalizing signal based on the detected mat selection state. When a specific mat is selected during precharge, the control circuit adjusts the timing of the equalizing signal to be released at an optimal moment that extends the effective precharge time while ensuring the signal is stable when needed. This dynamic parameter adjustment maintains both high-speed performance and signal reliability.
3Ease of manufacture
If conventional bit line equalizing circuits are used without mat selection-based control, then the circuit structure is simple, but the RAS precharge time cannot be optimized for high-speed memory applications
Solution Approach 1:
The patent applies local quality by introducing mat selection-based differential control into the bit line equalizing circuit. Instead of using a uniform equalization timing for all mats, the control circuit selectively applies different timing strategies based on which mat is being accessed. This localized control optimization enables high-speed performance for critical paths while maintaining simple circuit structures for non-critical operations, achieving a balance between complexity and speed.
Data Source
AI summary
A bit line equalizing control circuit of a semiconductor memory apparatus includes a control signal generating unit that receives a bank active signal to generate a control signal such that a bit line equalizing signal is delayed and enabled, a bit line equalizing selecting unit that generates a bit line equalizing detection signal in response to a plurality of mat select signals and the control signal, and a driver that receives the bit line equalizing detection signal to generate the bit line equalizing signal.