Bit Line Groove Structure for Low-Leakage Semiconductor Contacts
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Solution Overview
Problem
The existing semiconductor structures face issues with electric leakage between bit lines due to narrow bit line widths, leading to increased bit line contact resistance and reduced node contact window space, affecting the quality of the semiconductor structure.
Innovation Solution
A semiconductor structure and manufacturing method involving a laminated structure with a first conductive layer, a second conductive layer, and an insulating layer, where the first conductive layer fills a groove structure and covers the substrate, with a two-stage etching process to form a pattern structure, ensuring the bottom width of the pattern structure within the groove is not smaller than outside, thereby increasing the contact area and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the width of the bit line in the bit line contact hole is reduced to improve electric leakage prevention, then electric leakage between bit lines is reduced, but the bit line contact resistance increases
Solution Approach 1:
The patent applies different widths to different parts of the bit line structure: the bit line in the contact hole region has a smaller width to prevent electric leakage, while the bit line in the groove structure has a larger width to reduce contact resistance. This local differentiation of geometric properties resolves the contradiction between preventing leakage and maintaining low contact resistance.
2Reliability
If the bit line width on the substrate surface is increased to reduce contact resistance, then bit line contact resistance decreases, but the node contact window space is reduced
Solution Approach 1:
The bit line structure is segmented into different regions with different width characteristics. The groove structure creates a localized expansion of the bit line width specifically in the contact region, while the bit line width outside the groove remains smaller. This segmentation allows the contact resistance to be reduced without proportionally increasing the space occupied in the node contact window area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the contact area and reduces contact resistance between the pattern structure and the substrate, improving the quality of the semiconductor structure by maintaining a larger bottom width within the groove structure.
Implementation Method 1
In the first etching stage, a first etching gas is used for etching the first conductive material layer until the upper surface of the substrate is exposed
Implementation Method 2
in the second etching stage, a second etching gas is used for etching the first conductive material layer
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: a substrate with a groove structure formed therein is provided; a laminated structure is formed on the substrate, which includes a first conductive material layer, a second conductive material layer and an insulating material layer from bottom up, and the first conductive material layer fills the groove structure and covers the surface of the substrate; the insulating material layer, the second conductive material layer and the first conductive material layer are sequentially etched to form a bit line structure, in which a process of etching the first conductive material layer includes a first etching stage and a second etching stage, such that a bottom width of the first pattern structure located in the groove structure is not smaller than that of the first pattern structure located outside the groove structure.