Bit Line Implant Using Oxide-Nitride-Oxide Stack for Channel Length Control
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Solution Overview
Problem
Conventional semiconductor manufacturing methods face challenges in reducing design features and increasing manufacturing throughput for high-density and high-performance non-volatile memory devices, particularly in achieving smaller effective channel lengths for faster switching speeds.
Innovation Solution
A method involving the formation of bit line implants using a polysilicon and hard mask structure on an oxide-nitride-oxide stack, with precise spacing and dopant implantation to isolate semiconductor device regions, allowing for targeted bit line formation and reduced effective channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional manufacturing methods are used, then manufacturing throughput and reliability are maintained, but effective channel length cannot be sufficiently reduced for faster switching speeds
Solution Approach 1:
The patent segments the bit line formation process into multiple distinct stages: forming separate first and second conductive layers with different functions (bit line implant blocker vs. actual bit line), using an oxide-nitride-oxide stack as a multi-layer isolation structure, and creating spaced structures to define implant regions. This segmentation allows precise control of dopant implantation while maintaining manufacturing feasibility.
Solution Approach 2:
The patent introduces vertical layering with the oxide-nitride-oxide stack, moving from planar bit line formation to a three-dimensional structure where the bit line is formed at a specific depth within the stacked dielectric layers. This vertical dimension enables better isolation and precise spatial control of the implant process.
2Area of moving object
If design features are reduced for high density, then device density increases, but manufacturing precision requirements become more challenging
Solution Approach 1:
The patent changes the physical and chemical parameters of the bit line formation process by using low-energy ion implantation (5-30 KeV) with controlled dosage (1×10^12 to 1×10^15 atoms/cm²), forming conductive layers with specific thicknesses and material compositions. These parameter changes enable precise feature definition at reduced dimensions while maintaining manufacturing control.
Solution Approach 2:
The oxide-nitride-oxide stack serves as an intermediary structure that mediates between the substrate and the bit line conductive layers. This intermediate layer system provides isolation, defines implant boundaries, and enables precise spatial control of the bit line formation process at reduced feature sizes.
3Speed
If effective channel length is decreased for faster switching, then switching speed improves, but gate charge requirements increase
Solution Approach 1:
The patent applies local quality by creating highly doped bit line regions only in specific locations where needed for electrical connection, while maintaining undoped or lightly-doped regions elsewhere. The spaced structure configuration ensures dopant implantation is localized to precise areas, optimizing the balance between short channel length for speed and controlled doping for charge management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of bit lines with improved effective channel lengths, reducing gate charge requirements and enhancing switching speeds while maintaining manufacturing throughput and reliability.
Implementation Method 1
implanting a dopant at a dosage ranging from about 1×10^12 atoms/cm2 to about 1×10^15 atoms/cm2 and an implantation energy ranging from about 5 KeV to about 30 KeV between the first structure and the second structure
Data Source
AI summary
A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.