Bit-Line Input Synapse Array for Low-Power Spiking Neural Networks

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Solution Overview

Problem

Spiking neural networks (SNN) circuits face high power consumption during memory array operation, which hampers their energy efficiency and area utilization in edge computing applications.

Innovation Solution

The implementation of a bit-line input scheme in SNN circuits, featuring a bit-line input synapse array with page buffers, bit line transistors, memory cells, a word line, source lines, and source line transistors, reduces energy consumption and increases area efficiency by inputting data signals through bit lines, thereby minimizing power usage and enhancing memory array performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If word-line input scheme is used, then data can be input to memory array, but energy consumption is high and area efficiency is reduced

Engineering Contradiction:

Improveenergy consumptionVSAvoidarea efficiency

Core Design Contradiction:

Use of energy by moving objectVSArea of stationary object

Solution Approach 1:

The patent inverts the conventional word-line input approach by implementing bit-line input scheme. Instead of applying input signals to word lines and reading through bit lines, the patent applies data signals to bit lines and collects currents through source lines, fundamentally reversing the signal flow direction to achieve lower energy consumption and improved area efficiency

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the operational parameters of the memory array by modifying which lines receive input signals and which lines collect output currents. By switching from word-line activation to bit-line activation and from bit-line reading to source-line current collection, the patent achieves significant energy reduction while maintaining computational functionality

Inventive Principle:

Principle #35Parameter changes

2Productivity

If memory array operation is performed in SNN circuits, then neural network computation is enabled, but power consumption cannot be ignored

Engineering Contradiction:

Improvecomputation capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent replaces the conventional voltage-based read operation with a current-based current collection mechanism. By using source lines to collect currents that naturally flow through memory cells during bit-line input, the patent eliminates the need for additional read amplification circuits and associated power consumption, achieving energy-efficient neural network computation

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11551072B2Spiking neural networks circuit and operation method thereof

Publication Date: 2023.01.10 MACRONIX INTERNATIONAL CO LTD

AI summary

A spiking neural networks circuit and an operation method thereof are provided. The spiking neural networks circuit includes a bit-line input synapse array and a neuron circuit. The bit-line input synapse array includes a plurality of page buffers, a plurality of bit line transistors, a plurality of bit lines, a plurality of memory cells, one word line, a plurality of source lines and a plurality of source line transistors. The page buffers provides a plurality of data signals. Each of the bit line transistors is electrically connected to one of the page buffers. Each of the bit lines receives one of the data signals. The source line transistors are connected together. The neuron circuit is for outputting a feedback pulse.