Memory Bit Line Isolation Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Semiconductor memory devices manufactured using existing processes often suffer from parasitic capacitance due to poor isolation performance, which affects their electrical performance.
Innovation Solution
A semiconductor memory device manufacturing method that involves forming bit line structures and isolation structures on a substrate, with a dielectric layer filling the gaps between them. The method includes etching the dielectric layer to create contact holes and isolation structures, and forming an isolation layer on the side walls of both bit line and isolation structures to enhance isolation performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor contact structure is formed on a dielectric layer with a capacitor structure prepared on it to achieve conduction, then conduction between capacitor structure and active area is achieved, but parasitic capacitance occurs due to poor isolation performance
Solution Approach 1:
The patent divides the isolation structure into multiple segments: a first isolation structure formed on the dielectric layer, and a second isolation structure formed on the side wall of the first isolation structure. This segmentation creates multiple isolation zones that effectively reduce parasitic capacitance between adjacent bit line structures while maintaining conduction paths to active areas.
Solution Approach 2:
The patent applies different materials and structures at different locations: the first isolation structure uses a dielectric material filling the gap between bit lines, while the second isolation structure forms a side wall isolation layer. This local differentiation optimizes isolation performance at specific locations where parasitic capacitance is most problematic.
2Reliability
If isolation structures are added to reduce parasitic capacitance, then isolation performance improves, but device complexity increases
Solution Approach 1:
The patent combines the isolation function with the dielectric layer structure. The first isolation structure is formed by filling the dielectric material into the gap between adjacent bit line structures, merging the isolation function with the existing dielectric layer. The second isolation structure on the side wall further integrates isolation functionality into the vertical profile of the bit line structures.
Solution Approach 2:
The dielectric layer serves multiple functions: it acts as an insulating layer between bit line structures and as the first isolation structure. The second isolation structure on the side wall simultaneously provides isolation and defines the vertical boundary for subsequent processing steps, making the structure multi-functional.
Data Source
AI summary
The present disclosure provides a semiconductor memory device and a manufacturing method thereof. The manufacturing method includes: providing a substrate having a plurality of active areas; forming a plurality of bit line structures on the substrate, where the plurality of bit line structures are sequentially provided at intervals along a first direction; forming a dielectric layer on the substrate; etching the dielectric layer, to form a plurality of contact holes and a plurality of isolation structures, where each contact hole is between the adjacent bit line structures, the plurality of contact holes and the plurality of isolation structures are alternately provided along a second direction, the first direction is not parallel to the second direction; and forming an isolation layer on a side wall of each bit line structure and a side wall of each isolation structure.