Bit-Line Multiplexer Layout for Dense Semiconductor Memory
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Solution Overview
Problem
The downscaling of semiconductor storage devices has narrowed the distance between adjacent bit lines, necessitating a reduction in the placement area of decoders and multiplexers, which is challenging due to the increased number of bit lines and potential for increased parasitic capacitance and operational complexity.
Innovation Solution
The semiconductor storage device incorporates a configuration with first and second multiplexers, each comprising CMOS pairs and MOS pairs, which allow for efficient voltage application to selected and non-selected bit lines, reducing the number of transistors needed and minimizing the placement area while maintaining operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between bit lines is narrowed to increase storage density, then the storage capacity is improved, but the placement area of the decoder and multiplexer increases due to the increased number of bit lines
Solution Approach 1:
The patent combines the functions of multiple transistors into a shared configuration. Specifically, a first set of transistors is shared between the first multiplexer and the second multiplexer, and a second set of transistors is shared between the second multiplexer and the sense amplifier. This merging of functions reduces the total transistor count and consequently reduces the placement area of the decoder and multiplexer, allowing for narrower bit line spacing and increased storage density.
2Productivity
If the number of transistors in the multiplexer is increased to handle more bit lines, then the operational efficiency is improved, but the placement area and parasitic capacitance increase
Solution Approach 1:
The patent implements multi-functionality by designing the second multiplexer to serve dual purposes: it selectively connects bit lines to the sense amplifier during read operations and also applies non-select voltages to bit lines during write operations. Additionally, the first and second sets of transistors are shared across multiple functional blocks (multiplexers and sense amplifier), reducing the overall transistor count while maintaining the ability to handle multiple bit lines efficiently.
3Speed
If the transistor count in the multiplexer is reduced to decrease parasitic capacitance, then the write and read operation speed is improved, but the ability to handle multiple bit lines is compromised
Solution Approach 1:
The patent segments the multiplexer functionality into distinct transistor sets with specific roles. The first set of transistors is dedicated to selectively connecting bit lines during read operations, while the second set of transistors handles applying non-select voltages during write operations. This segmentation allows each transistor set to be optimized for its specific function, reducing unnecessary parasitic capacitance while maintaining the ability to handle multiple bit lines through the shared configuration.
Data Source
AI summary
A device includes a memory-cell array and a sense-amplifier. A decoder connects a first BL to the sense amplifier. The decoder includes first and second multiplexers. The first multiplexer includes a first n-type transistor and a first p-type transistor. The first n-type transistor is connected to the first BL and capable of applying a first voltage for writing a first logic or a non-select voltage for not writing data to the first BL. The first p-type transistor is connected to the first BL and capable of applying a second voltage for writing a second logic or the non-select voltage to the first BL. The second multiplexer is connected between the first multiplexer and the sense amplifier and transmits the first voltage or the non-select voltage to the first n-type transistor and transmits the second voltage or the non-select voltage to the first p-type transistor.