Bit Line Multiplexer Circuit for Low-Delay Memory Readout
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Solution Overview
Problem
Existing memory devices face challenges in reducing bit line loading and read delay while maintaining low periphery area and leakage, particularly in multiplexing operations for non-volatile memory devices like MRAM, which are crucial for lower level caches.
Innovation Solution
A write-read circuit with a multiplexer that includes select devices with divided transistors for read and write operations, allowing independent control of transistors to reduce capacitive loading during read operations without increasing multiplexer dimensions, using a ratio of transistor widths to manage current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the multiplexer size is increased to provide sufficient write current, then write current is improved, but bit line loading and read delay increase
Solution Approach 1:
The multiplexer is segmented into two separate multiplexers: a first multiplexer for write operations and a second multiplexer for read operations. Each multiplexer is optimized independently for its specific function, allowing the write multiplexer to be sized for sufficient write current while the read multiplexer remains small to minimize bit line loading and read delay.
2Loss of time
If the multiplexer size is decreased to reduce bit line loading, then read delay is improved, but write current becomes insufficient
Solution Approach 1:
The multiplexer is segmented into two separate multiplexers: a first multiplexer for write operations and a second multiplexer for read operations. Each multiplexer is optimized independently for its specific function, allowing the read multiplexer to be sized small for minimal bit line loading while the write multiplexer is sized for sufficient write current.
3Loss of energy
If the periphery area is increased to reduce multiplexer dimensions, then bit line loading is reduced, but periphery area and leakage increase
Solution Approach 1:
Each multiplexer is designed to be multi-functional in terms of operation timing - the first multiplexer handles write operations during write cycles and the second multiplexer handles read operations during read cycles. This functional separation allows both multiplexers to be optimized for their specific operations without requiring additional area for separate dedicated circuits.
Data Source
AI summary
A memory device with multiplexers for multiplexing write and read operations to bit lines is provided. In one aspect, a write-read circuit includes a multiplexer for multiplexing the write and read operations. The multiplexer includes a plurality of select devices, each select device being associated with one of a plurality of bit lines, and each select device including a first transistor and a second transistor. The write-read circuit further includes a controller configured to, for a write operation using a particular bit line, control the multiplexer to turn on both transistors of the first select device associated with the particular bit line, and for a read operation using the particular bit line, control the multiplexer to turn on the first transistor and turn off the second transistor of the first select device associated with the particular bit line.