Bit Line Sense Amplifier Offset Compensation for Faster Memory Sensing
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Solution Overview
Problem
Semiconductor memory devices face issues with loading mismatch between bit lines and complementary bit lines, and threshold voltage mismatch between transistors, leading to decreased sensing efficiency and speed in bit line sense amplifiers.
Innovation Solution
A bit line sense amplifier configured as a single-ended sense amplifier with a differential amplifier, sensing inverter, and switches for offset compensation, reducing capacitance load through feedback of converted signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high capacity is implemented in semiconductor memory devices, then storage capacity increases, but loading mismatch between bit line and complementary bit line occurs, decreasing sensing efficiency
Solution Approach 1:
The patent extracts the offset compensation function from the main sensing operation by introducing a separate offset compensation circuit that operates independently. This circuit removes the offset voltage between bit line and complementary bit line before the main sensing operation, allowing high capacity implementation without sensing efficiency degradation.
Solution Approach 2:
The patent introduces an intermediary offset compensation circuit between the bit line and the sense amplifier. This intermediary component compensates for loading mismatch by adjusting the offset voltage, enabling the system to handle high capacity while maintaining sensing efficiency.
2Quantity of substance
If micro processes are used to increase transistor density, then device capacity increases, but threshold voltage mismatch between transistors occurs, decreasing sensing speed
Solution Approach 1:
The patent performs offset compensation as a preliminary action before the main sensing operation. By compensating for threshold voltage mismatch in advance through the offset compensation circuit, the system maintains sensing speed despite increased transistor density from micro processes.
3Reliability
If conventional differential sense amplifier is used, then sensing operation is performed, but capacitance load on input signal is high, reducing offset compensation efficiency
Solution Approach 1:
The patent segments the sensing operation into two distinct phases: offset compensation phase and main sensing phase. During offset compensation, the capacitance load is minimized by using only essential components, while during main sensing, the full differential amplifier functionality is engaged. This segmentation reduces overall capacitance load and improves offset compensation efficiency.
Data Source
AI summary
A bit line sense amplifier includes a differential amplifier configured to receive an input signal from a bit line through an input terminal of the bit line sense amplifier and output a first signal to a first node of the bit line sense amplifier, a sensing inverter configured to receive the first signal and output a second signal to a second node of the bit line sense amplifier, the second signal resulting from inverting the first signal, a first switch configured to electrically connect the second node to a positive input of the differential amplifier, a second switch configured to electrically connect the first node to the positive input of the differential amplifier, and a third switch configured to electrically connect the second node to a negative input of the differential amplifier.