Memory Bit Line and Gate Structure With Oxidized Contact Interfaces
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Solution Overview
Problem
The challenge in semiconductor memory devices is to enhance the integration and density of memory cells while improving the structural reliability and efficiency of bit lines and gate structures, which is complicated by the presence of voids in bit line contacts and the complexity of current fabrication processes.
Innovation Solution
The solution involves forming bit lines and gate structures with a composite semiconductor layer, including a first and second oxidized interface layer, where the second oxidized interface layer is higher than the first, to improve the structural reliability and performance by addressing the issues of voids in bit line contacts and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to meet high integration requirements, then storage capacity is improved, but the difficulty and complexity of fabricating processes increases
Solution Approach 1:
The bit line structure is segmented into multiple functional layers: semiconductor layer, conductive layer, and covering layer. This segmentation allows each layer to perform specific functions and simplifies the overall fabrication process by enabling modular manufacturing of complex high-density memory structures
Solution Approach 2:
The bit line is constructed as a composite structure with semiconductor layer, conductive layer, and covering layer. This composite approach enables high memory cell density while maintaining manageable fabrication complexity through standardized multi-layer processing techniques
2Ease of manufacture
If bit line contact structure is simplified for easier manufacturing, then ease of manufacture is improved, but structural reliability deteriorates due to voids and protrusions
Solution Approach 1:
The bit line contact structure implements local quality differentiation through the covering layer that specifically addresses the contact region. This localized structural enhancement improves reliability at critical contact points while maintaining ease of manufacture through standardized multi-layer processing
Solution Approach 2:
The bit line contact is formed as a composite structure with semiconductor layer, conductive layer, and covering layer. This composite design eliminates voids and protrusions that plague simpler single-layer contacts, achieving both ease of manufacture and high reliability
3Reliability
If oxidized interface layers are added to improve contact reliability, then structural reliability is improved, but device complexity increases
Solution Approach 1:
The oxidized interface layers are merged into the existing multi-layer bit line structure as integral components rather than separate additions. The first oxidized interface layer between bit line contact and semiconductor layer, and the second oxidized interface layer within the gate structure semiconductor layer, are formed through the same fabrication process sequence, maintaining reliability improvement without proportionally increasing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the structural reliability and performance of semiconductor devices by reducing the impact of voids in bit line contacts and improving the integration and density of memory cells, leading to more efficient and reliable semiconductor memory devices.
Implementation Method 1
a first oxidized interface layer is formed between each of the bit line contacts and the semiconductor layer of each of the bit lines
Data Source
AI summary
The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.