Bit Line Pre-Charge Circuit with Dummy Array for Memory
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Solution Overview
Problem
In large capacity semiconductor memory devices, the increased length of bit lines leads to higher resistance and parasitic capacitance, resulting in longer time constants and slower pre-charging of bit lines, which negatively impacts memory performance.
Innovation Solution
A bit line pre-charge circuit that includes a voltage generator and a dummy array system, where the dummy array replicates the parasitic RC characteristics of the bit lines, allowing for dynamic adjustment of the pre-charge voltage to compensate for resistance and capacitance changes along the bit lines, thereby improving pre-charging speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the length of bit lines is extended to increase storage capacity, then the storage capacity is improved, but the resistance and parasitic capacitance of bit lines increase, resulting in longer pre-charge time
Solution Approach 1:
The patent applies preliminary action by introducing a dummy array that replicates the parasitic RC characteristics of the actual bit lines before the real bit lines are pre-charged. This dummy array is pre-configured with equivalent resistance and capacitance values, allowing the pre-charge circuit to be optimized based on the dummy array's characteristics rather than the actual extended bit lines, thereby reducing the pre-charge time for the real bit lines.
Solution Approach 2:
The patent uses copying by creating a dummy array that is a replica of the actual memory array, with dummy bit lines that have the same parasitic RC characteristics as the real bit lines. This copy allows the system to model and measure the effects of long bit lines without actually extending the real bit lines, enabling optimization of pre-charge circuits based on the dummy array's known characteristics.
2Quantity of substance
If the length of bit lines is extended to increase storage capacity, then the storage capacity is improved, but the resistance and parasitic capacitance of bit lines increase, resulting in higher RC time constant
Solution Approach 1:
The patent creates a dummy array that copies the parasitic RC characteristics of the actual extended bit lines. The dummy bit lines are designed with equivalent resistance and capacitance values, allowing the system to model the RC time constant behavior without actually having the full complexity of extended real bit lines. This simplifies the design process for optimizing pre-charge circuits.
Solution Approach 2:
The dummy array is pre-configured with known RC characteristics that match the expected behavior of extended bit lines. This preliminary configuration allows engineers to calculate and optimize pre-charge voltages and timing parameters based on the dummy array's simplified, known characteristics rather than dealing with the complex, variable RC time constants of actual extended bit lines.
3Device complexity
If a fixed pre-charge voltage is used for all bit lines, then the circuit design is simplified, but the pre-charging speed varies due to different parasitic RC characteristics along bit lines
Solution Approach 1:
The patent applies local quality by adjusting the pre-charge voltage based on the specific parasitic RC characteristics of different bit line segments. The dummy array allows measurement of local RC characteristics at different positions along the bit lines, enabling the system to apply different pre-charge voltages to different regions. This ensures that each bit line segment receives the appropriate pre-charge voltage to achieve optimal pre-charging speed.
Solution Approach 2:
The dummy array serves as a feedback mechanism by providing known RC characteristic data that can be used to adjust pre-charge voltages. The measured characteristics from the dummy array feed back into the design of pre-charge circuits, allowing for iterative optimization of pre-charge voltages based on actual or simulated bit line conditions, thereby improving pre-charging speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the transient response during bit line pre-charging, reducing the time required to reach the pre-charge voltage and improving memory performance by dynamically adjusting the pre-charge voltage based on the parasitic RC characteristics of the bit lines.
Implementation Method 1
the parasitic capacitance C between the bit lines to increase
Implementation Method 2
the resistance value R of the bit line to increase
Implementation Method 3
the parasitic capacitance C between the bit lines to increase
Implementation Method 4
the resistance value R of the bit line to increase
Data Source
AI summary
Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. An example pre-charge circuit includes a voltage generator configured to generate an output voltage having a magnitude based at least in part on a reference voltage and a feedback signal, first and second drivers, and a voltage detector. The voltage detector is configured to determine a voltage difference between the reference voltage and a sample voltage of a data line coupled to the second driver and generate the feedback signal based at least in part on the difference.