Multi-Stage Bit Line Pre-Charge for Fast Reads Without Disturbance

Solution Overview

Problem

Existing memory technologies face challenges in achieving high-speed read operations due to untimely pre-charge control signals, leading to anomalous bit cell behavior and data disturbances during read operations, particularly due to coupling between charging bit lines and word lines.

Innovation Solution

Implementing a multi-stage pre-charge circuit with individually controllable first and second pre-charge components, where the first component begins pre-charging before the read operation concludes and the second component takes over after, minimizing coupling and ensuring rapid recharging of bit lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If pre-charge control signal is activated before read operation concludes, then read operation speed is improved, but coupling between charging bit lines and word lines causes anomalous bit cell behavior and data disturbances

Engineering Contradiction:

Improveread operation speedVSAvoiddata integrity

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The pre-charge circuit is divided into two distinct stages with separate control signals. The first pre-charge component is activated before the read operation concludes to begin recharging the bit line, while the second pre-charge component is activated after the read operation to complete the charging process. This segmentation allows the bit line to start recharging during the read operation without causing coupling-induced disturbances, as the second component takes over after the read operation completes, ensuring data integrity is maintained.

Inventive Principle:

Principle #1Segmentation

2Productivity

If single-stage pre-charge circuit is used, then device complexity is reduced, but bit line recharging speed is insufficient for high-speed read operations

Engineering Contradiction:

Improvebit line recharging speedVSAvoidpre-charge circuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The pre-charge circuit is divided into two distinct stages with separate control signals. The first pre-charge component is activated before the read operation concludes to begin recharging the bit line, while the second pre-charge component is activated after the read operation to complete the charging process. This segmentation allows the bit line to start recharging during the read operation without causing coupling-induced disturbances, as the second component takes over after the read operation completes, ensuring data integrity is maintained.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first pre-charge component is activated before the read operation concludes to begin recharging the bit line in advance. This preliminary action ensures that the bit line starts recharging during the read operation, reducing the total recharging time and enabling high-speed read operations without requiring a complex single-stage circuit.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250364022A1Multi-Stage Bit Line Pre-Charge

Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.