Bit Line Precharge Circuit for Memory Program Operation Time Reduction

Solution Overview

Problem

Current memory devices require precharging and discharging of bit lines during both program and verify phases, leading to increased overall program operation time due to repeated charging and discharging cycles.

Innovation Solution

A memory device and method that precharge bit lines without discharging during both program and verify phases by maintaining the precharge voltage levels throughout, reducing the need for repeated charging and discharging operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bit lines are precharged and discharged during both program and verify phases, then verification can be performed, but overall program operation time increases due to repeated charging and discharging cycles

Engineering Contradiction:

Improveverification operationVSAvoidprogram operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The bit line is precharged to a first voltage level before the program operation begins. This preliminary charging action is maintained through both the program phase and the verify phase, eliminating the need for repeated charging cycles. The precharge circuit maintains the voltage level without discharging, thereby reducing overall operation time while ensuring verification can still be performed.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuous maintenance of the bit line voltage level from the program phase through the verify phase without interruption. The precharge circuit continues to hold the voltage level throughout both operations, creating a continuous useful action that eliminates the wasted time of repeated charging and discharging cycles while maintaining verification capability.

Inventive Principle:

Principle #20Continuity of useful action

2Reliability

If bit lines are repeatedly precharged and discharged, then verify operation can be performed, but the number of operation cycles increases

Engineering Contradiction:

Improveverify operationVSAvoidoperation efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The bit line is precharged to a first voltage level before the program operation begins. This preliminary charging action is maintained through both the program phase and the verify phase, eliminating the need for repeated charging cycles. The precharge circuit maintains the voltage level without discharging, thereby reducing overall operation time while ensuring verification can still be performed.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuous maintenance of the bit line voltage level from the program phase through the verify phase without interruption. The precharge circuit continues to hold the voltage level throughout both operations, creating a continuous useful action that eliminates the wasted time of repeated charging and discharging cycles while maintaining verification capability.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11501836B2Memory device for controlling voltage of bit line and method of operating the same

Publication Date: 2022.11.15 SK HYNIX INC

AI summary

The present technology relates to an electronic device. A memory device capable of reducing a time consumed in a program operation includes a memory cell array, a page buffer group connected to the memory cell array through a plurality of bit lines and a voltage generator configured to generate voltages to apply to each of a plurality of page buffers included in the page buffer group. Each of the plurality of page buffers includes a precharge circuit that controls potential levels of the plurality of bit lines to be maintained at precharge levels.