Bit Line Pre-charge Ramp Rate Control for Flash Memory
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Solution Overview
Problem
Flash storage devices experience higher peak and average currents during the middle of a program operation due to increased inter-bit line capacitances and fast voltage ramping rates, leading to significant voltage drops and impacting write performance.
Innovation Solution
A storage device controller adjusts bit line pre-charging ramp rates and target voltages based on data latch counts, pre-charging at slower rates to larger target voltages during the middle of a program operation and at faster rates to smaller target voltages at the beginning and end, to balance power consumption and write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit lines are pre-charged at fast ramp rates to maintain write performance, then write speed is improved, but peak current increases causing voltage drops
Solution Approach 1:
The patent implements dynamic ramp rate adjustment by monitoring the number of inhibited bit lines and adapting the pre-charge ramp rate accordingly. When few bit lines are inhibited, a fast ramp rate is used to maintain write performance. When many bit lines are inhibited, the ramp rate is reduced to limit peak current, thus dynamically optimizing between speed and power consumption.
Solution Approach 2:
The controller changes the ramp rate parameter based on the inhibition count of bit lines. By adjusting this electrical parameter dynamically during the program operation, the system optimizes the balance between write speed and peak current consumption, preventing voltage drops while maintaining performance where possible.
2Stability of the object's composition
If bit lines are pre-charged to larger target voltages to reduce current, then voltage stability is improved, but pre-charge time increases
Solution Approach 1:
The system dynamically adjusts the target voltage based on how many bit lines are inhibited. When many bit lines are inhibited, a larger target voltage is used to reduce current consumption and improve voltage stability. When few bit lines are inhibited, a smaller target voltage is used to minimize pre-charge time, thus dynamically optimizing between stability and speed.
Solution Approach 2:
The controller changes the target voltage parameter according to the inhibition count. This parameter adjustment allows the system to balance voltage stability requirements against time constraints, using higher voltages only when necessary to reduce current during high-inhibition phases.
3Reliability
If average current is reduced to extend flash memory life, then reliability is improved, but voltage levels may drop below functional thresholds
Solution Approach 1:
The controller adjusts the target voltage parameter to ensure that even when average current is reduced for reliability, the voltage remains above the functional threshold required for proper operation. This parameter optimization allows extended memory life while maintaining functionality.
Solution Approach 2:
The system uses feedback from the inhibition count to dynamically adjust operating parameters. This closed-loop control ensures that current reduction for reliability does not push voltage below functional thresholds, as the controller adapts based on real-time conditions.
Data Source
AI summary
Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge ramp rate control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory at a first ramp rate to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines at a second, faster ramp rate to a second, smaller target voltage. The inhibit bit line count may increase throughout a program operation, and the bit line count range may be configured for the middle of the program operation where current is typically high. Thus, a balance in power consumption and performance may be achieved during program operations using ramp rate control.