Memory Storage Bit Line Pre-Charge for Read Speed
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Solution Overview
Problem
The development of faster clock rates in memory storage apparatuses is bottlenecked by the slow reading speed, which is limited by the time-consuming pre-charge operation required for bit lines during reading operations.
Innovation Solution
The memory storage apparatus performs a pre-charge operation to part or all of the bit lines when enabling the word lines, reducing the pre-charge time and enhancing reading speed by establishing pre-charge paths through hierarchical methods and simultaneous pre-charging of bit and data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock rate is increased to improve data transmission speed, then the data transmission rate is improved, but the reading speed becomes the bottleneck and cannot be enhanced accordingly
Solution Approach 1:
The patent performs pre-charge operations to bit lines in advance, before the actual read operation is initiated. By pre-charging the bit lines during the period when word lines are being enabled, the system prepares the necessary signal paths beforehand, eliminating the need to wait for bit line charging during the critical read path, thus enabling faster reading that keeps pace with higher clock rates
2Speed
If the pre-charge operation time is reduced to accelerate reading speed, then the reading speed is improved, but the bit lines may not be fully charged leading to reading errors
Solution Approach 1:
The system performs the pre-charge operation during the word line enable period, which is before the actual data read operation. This preliminary charging ensures that when the read operation commences, the bit lines are already charged to the appropriate voltage levels, maintaining reading accuracy while allowing the overall read time to be reduced
Solution Approach 2:
The patent overlaps the pre-charge operation with the word line enable operation, making these two necessary actions occur simultaneously rather than sequentially. This continuous utilization of operational windows ensures that no time is wasted, the bit lines are properly charged, and the reading operation can proceed immediately without interruption or extended waiting time
Data Source
AI summary
A memory storage apparatus including a plurality of word lines, a plurality of bit lines, a memory cell array, and a memory controller is provided. The memory cell array includes a plurality of memory cells. The memory cells are configured to store data. Each of the memory cells is coupled to the corresponding word line and the corresponding bit line. The memory controller is configured to perform a read operation to the memory cell array. The memory controller performs a pre-charge operation to part or all of the bit lines when the memory controller enables the word lines. In addition, an operating method of a memory storage apparatus is also provided.