Bit Line Resistance Compensation in NAND Flash Memory
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Solution Overview
Problem
NAND flash memory technologies face challenges in compensating for variations in bit line resistance, which lead to increased effective threshold voltage distributions and variability in memory cell sensing due to manufacturing and lithography-related issues, affecting the reliability and accuracy of data storage and retrieval.
Innovation Solution
The approach involves determining a plurality of bit line read voltages for different zones within a memory die or plane based on sensing criteria, such as fail bits, to compensate for die-to-die and plane-to-plane variations in bit line resistance. This includes interpolating bit line read voltages and applying specific voltages to different bit line groupings to account for systematic process variations, thereby stabilizing the sensing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process geometries are shrunk to reduce cost per bit, then storage capacity increases, but bit line resistance increases and variability increases
Solution Approach 1:
The memory array is divided into multiple zones, each with its own dedicated sense amplifier. This segmentation allows independent optimization and compensation for bit line resistance variations in each zone, addressing the reliability issue caused by scaling while maintaining high storage capacity.
Solution Approach 2:
Different sense amplifiers are configured with different compensation parameters tailored to their specific zone's bit line characteristics. This local quality approach ensures that each zone receives customized compensation for its resistance variability, improving overall reliability without sacrificing the high-density storage achieved through scaling.
2Measurement precision
If bit line resistance variations are compensated using traditional methods, then sensing accuracy improves, but threshold voltage distributions become broader
Solution Approach 1:
The invention dynamically adjusts sense amplifier parameters including reference voltages, compensation voltages, and timing parameters based on the specific zone and operating conditions. This parameter optimization allows accurate sensing while maintaining tight threshold voltage distributions, resolving the contradiction between sensing accuracy and manufacturing precision.
Solution Approach 2:
The system incorporates feedback mechanisms where sense amplifier outputs are used to adjust compensation parameters for subsequent operations. This feedback loop enables real-time optimization of sensing accuracy while preventing threshold voltage distribution broadening, as the system learns and adapts to actual bit line resistance characteristics.
3Reliability
If multiple sense amplifiers are used for different zones, then bit line resistance compensation improves, but device complexity increases
Solution Approach 1:
The sense amplifiers are designed with universal multi-functional capabilities, where a single sense amplifier structure can serve multiple zones through reconfiguration of its compensation parameters and reference voltages. This universality reduces device complexity compared to having completely separate sense amplifiers for each zone, while still providing zone-specific resistance compensation.
Data Source
AI summary
Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning.