Bit Line Section Precharge for Memory Read Stability
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Solution Overview
Problem
Existing memory devices face reduced read stability due to large variability in transistor sizes, leading to decreased static noise margin and increased manufacturing costs, with previous attempts to reduce bit line voltage being sensitive to process, voltage, and temperature variations.
Innovation Solution
A memory device with a bit line divided into sections, where one section is precharged to a first voltage and another to a second voltage, with a charge-sharing circuit to couple and decouple these sections, achieving a final bit line voltage between the two, independent of manufacturing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bit line voltage is reduced to improve read stability, then the static noise margin improves, but the sensitivity to process, voltage, and temperature variations increases
Solution Approach 1:
The bit line is divided into two separate sections: a first section precharged to a first voltage and a second section precharged to a second voltage. This segmentation allows independent voltage control of each section, enabling the charge-sharing circuit to achieve a precise final bit line voltage that improves read stability while reducing sensitivity to PVT variations through the balanced charge-sharing mechanism.
Solution Approach 2:
A charge-sharing circuit is introduced as an intermediary mechanism between the first and second bit line sections. This circuit selectively couples the two sections to share charge, achieving a final bit line voltage that is a function of both precharge voltages. The charge-sharing circuit acts as a buffer that reduces sensitivity to PVT variations while maintaining improved read stability.
2Reliability
If multiple supply voltages or NMOS devices are used to reduce bit line voltage, then read stability improves, but manufacturing cost and device complexity increase
Solution Approach 1:
The charge-sharing circuit serves multiple functions: it acts as a voltage regulator to achieve the desired bit line voltage, functions as a buffer to reduce PVT sensitivity, and eliminates the need for separate NMOS precharge devices or multiple supply voltages. This multi-functionality reduces device complexity while maintaining read stability improvements.
Solution Approach 2:
The invention changes the voltage parameter of the bit line by using a charge-sharing mechanism between two precharged sections rather than using threshold voltage drops from NMOS devices. This parameter change approach achieves voltage reduction without requiring low-threshold-voltage NMOS devices, special masks, or additional supply voltages, thereby reducing manufacturing cost and complexity.
3Ease of operation
If the bit line is precharged to supply voltage before access, then the memory operation is simplified, but the static noise margin is reduced
Solution Approach 1:
The bit line sections are precharged to specific voltages before the memory access operation. The first section is precharged to a first voltage and the second section to a second voltage, preparing the charge-sharing mechanism in advance. This preliminary voltage preparation enables the charge-sharing circuit to achieve the optimal bit line voltage during access, improving static noise margin while maintaining operational simplicity.
Solution Approach 2:
The bit line voltage is made dynamic through the charge-sharing mechanism. During the access operation, the charge-sharing circuit selectively couples the two precharged sections, allowing the bit line voltage to transition from the precharge state to the operational state. This dynamic voltage adjustment improves static noise margin during the critical read window while maintaining ease of operation through automated charge-sharing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves read stability by reducing bit line voltage, enhances design robustness, and reduces sensitivity to process and temperature variations, while maintaining cost-effectiveness by using a single supply voltage.
Implementation Method 1
a charge-sharing circuit selectively coupled to the first section and the second section, in which the charge-sharing circuit is configured to couple and decouple the first section to the second section
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell (34). A reduction in bit line voltage is achieved by precharging different sections (31, 33) of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference (B2-C2) between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.