Bit Line Selection Circuit Shielding for Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND flash memory bit line selection methods struggle with miniaturization and reliability due to floating gate coupling between memory cells and bit lines, which affects noise suppression during reading operations.
Innovation Solution
The semiconductor storage device configures a bit line selection circuit in the memory cell array to select bit line pairs composed of an even-numbered and an odd-numbered bit line, with adjacent non-selected bit lines shielding the selected pair and interposing two non-selected bit lines to reduce coupling effects, using a current-type sensing method to enhance noise suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the bit line selection circuit is formed in the memory cell array to achieve miniaturization, then the integration density is improved, but the floating gate coupling between memory cells and bit lines increases causing noise and reliability degradation
Solution Approach 1:
The bit line selection circuit is segmented into multiple independent selection units, each handling specific bit lines. This segmentation allows for localized control and reduces the overall coupling effect while maintaining miniaturization benefits.
Solution Approach 2:
Dummy bit lines are introduced as intermediary elements between the selected bit lines and the memory cell array. These dummy bit lines act as shields that block the capacitive coupling path, reducing noise from floating gate effects while allowing the bit line selection circuit to remain integrated in the memory cell array.
2Reliability
If conventional alternating sensing of even and odd bit lines is used, then noise suppression is improved, but the bit line selection circuit cannot be miniaturized
Solution Approach 1:
The even and odd bit line selection functions are merged into a single integrated bit line selection circuit located within the memory cell array. The circuit uses shared components and coordinated control signals to achieve both even and odd bit line selection, eliminating the need for separate selection circuits and enabling miniaturization while maintaining noise suppression capabilities.
Solution Approach 2:
Dummy bit lines serve as intermediary shielding elements that enable the merged bit line selection circuit to suppress noise from floating gate coupling. These intermediaries block capacitive interference paths, allowing the compact integrated circuit to achieve noise suppression performance comparable to conventional alternating sensing methods.
3Productivity
If bit lines are closely integrated in the memory cell array, then integration density is improved, but capacitive coupling between bit lines increases causing sensing errors
Solution Approach 1:
Dummy bit lines are positioned between adjacent functional bit lines to act as capacitive shields. These intermediary elements reduce the direct capacitive coupling between bit lines by providing a grounded reference plane, thereby maintaining high integration density while preventing sensing errors caused by signal interference.
Solution Approach 2:
The bit line structure is designed with local quality variations where dummy bit lines are strategically placed in high-interference regions. This creates localized shielding zones that reduce capacitive coupling precisely where integration density is highest, maintaining sensing precision in critical areas while preserving overall integration benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high integration and improved reliability by minimizing the impact of floating gate coupling and capacitive noise, allowing for accurate and efficient bit line sensing.
Implementation Method 1
floating gate (FG) coupling between memory cells or coupling between bit lines
Data Source
AI summary
The disclosure provides a semiconductor storage device that realizes high integration and improves reliability. A bit line selection circuit (100) of a flash memory includes transistors (BLSeO, BLSeE, BLSoO, BLSoE) in the column direction of bit lines (BL0-BL3), selecting a bit line pair composed of an even-numbered bit line (BL0) and an odd-numbered bit line (BL3) is selected by the transistors, in which a bit line pair (BL1, BL2) adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair (BL0, BL3) is connected to page buffer/sensing circuit through an output node (BLS0, BLS1).