Self-Assembled Bit-Line Contact Formation

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Solution Overview

Problem

The increasing feature density in semiconductor devices necessitates advanced lithography techniques and expensive equipment, leading to higher fabrication costs and complexity, particularly due to the need for multiple patterning and alignment challenges in forming high-density contact features.

Innovation Solution

A self-assembled contact formation scheme that eliminates the need for dedicated photo-masks by using bit-line structures as self-assembled masks, reducing fabrication complexity and costs through oblique bit-line trench formation and spacer structures to facilitate vertical electrical connections without additional interconnect components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If multiple patterning lithography techniques are used to form high-density contact features, then device density is improved, but fabrication complexity and costs increase due to multiple photo-masks and alignment challenges

Engineering Contradiction:
Improvedevice densityVSAvoidfabrication complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The bit-line structure serves as its own mask during the formation of contact features. The oblique bit-line trench automatically defines the contact opening positions through its geometry, eliminating the need for separate photo-masks and reducing fabrication steps while maintaining high device density

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The bit-line trench is formed with an oblique angle in advance, which pre-defines the contact opening locations. This preliminary geometric configuration enables subsequent self-aligned contact formation without requiring additional patterning steps or alignment procedures

Inventive Principle:
Principle #10Preliminary action

2Area of moving object

If multiple photo-masks and etch mask layers are used to define high-density features, then feature density is improved, but fabrication costs increase

Engineering Contradiction:
Improvefeature densityVSAvoidfabrication cost
Core Design Contradiction:
Area of moving objectVSEase of manufacture

Solution Approach 1:

The bit-line structure performs multiple functions: it serves as both the interconnect line and as the mask for defining contact features. This multi-functionality eliminates the need for separate photo-masks and reduces the number of fabrication steps, thereby lowering manufacturing costs while achieving high feature density

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The masking function is merged into the bit-line structure itself. The oblique trench geometry combines the interconnect formation and contact definition processes into a single integrated step, eliminating the need for separate photo-masking operations and reducing overall fabrication complexity

Inventive Principle:
Principle #5Merging (Combining)

3Area of moving object

If multiple photo-masks are used for high-density contact formation, then contact density is improved, but reliability decreases due to alignment and overlay challenges

Engineering Contradiction:
Improvecontact densityVSAvoidalignment reliability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The bit-line trench automatically defines contact opening positions through its own geometry. This self-aligned approach eliminates overlay errors between separate photo-masks, ensuring high alignment reliability while achieving the required contact density for advanced device nodes

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11502087B2Semiconductor structure and method for fabricating the same
Publication Date: 2022.11.15 XIA TAI XIN SEMICON QING DAO LTD
  • US11502087B2 patent drawing
  • US11502087B2 patent drawing
  • US11502087B2 patent drawing

AI summary

A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor device comprises: a first active region over a substrate; and a first bit line structure intercepting the first active region at a level that is lower than a top-most surface thereof, the first bit line structure including a barrier liner having a U-profile in a width direction thereof in electrical contact with the first active region.