Bit Line Sense Amplifier Voltage Compensation Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices face issues during testing due to legacy test conditions that can lead to 'false-positives' (non-defective units being treated as defective, reducing production yield) due to voltage level reductions in bit lines before sensing control signals are enabled, caused by parasitic bridge resistors and pre-charge operations.
Innovation Solution
A bit line sense amplifier with a sense amplifying circuit, power supply voltage providing circuit, and bit line voltage compensation circuit to maintain voltage levels above a threshold after pre-charging, using bit line sensing control signals to prevent voltage reduction and ensure accurate sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If legacy test conditions are used for testing conventional semiconductor memory devices, then test compatibility with older devices is maintained, but false-positive defects increase reducing production yield
Solution Approach 1:
The patent applies dynamics by making the power supply voltage to bit lines dynamic rather than static. The bit line voltage is adjusted based on the timing of sensing operations - maintained at a higher level during testing and reduced during normal operation. This dynamic voltage adjustment allows the system to adapt to different operational modes (testing vs. normal operation) and eliminates false positives during testing while maintaining compatibility with legacy test conditions.
2Ease of operation
If pre-charge operations are performed on bit lines, then bit lines are prepared for sensing, but voltage levels drop below sensing threshold before sensing control signals are enabled
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines to a voltage level higher than the normal sensing threshold before the sensing operation begins. This preliminary over-charging compensates for the voltage drop that occurs during the delay period between pre-charge completion and sensing signal activation. By anticipating the voltage drop and compensating in advance, the bit lines maintain adequate voltage levels for accurate sensing when the sensing operation actually begins.
3Manufacturing precision
If sensing control signals are delayed after pre-charge completion, then charge sharing is sufficient, but parasitic bridge resistors cause voltage reduction leading to false defect detection
Solution Approach 1:
The patent applies parameter changes by modifying the voltage parameter of the bit lines during the delay period. Instead of maintaining a constant voltage, the bit line voltage is elevated above the normal operating level during the delay between pre-charge completion and sensing activation. This parameter change compensates for the harmful effects of parasitic bridge resistors during the delay period, allowing sufficient charge sharing time without causing false defect detection.
Data Source
AI summary
A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.